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x64: cpu_wait: Remove magic values
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@ -26,21 +26,26 @@ constexpr auto PauseCycles = 100'000U;
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#ifdef _MSC_VER
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#ifdef _MSC_VER
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__forceinline static void TPAUSE() {
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__forceinline static void TPAUSE() {
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_tpause(0, FencedRDTSC() + PauseCycles);
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static constexpr auto RequestC02State = 0U;
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_tpause(RequestC02State, FencedRDTSC() + PauseCycles);
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}
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}
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__forceinline static void MWAITX() {
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__forceinline static void MWAITX() {
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static constexpr auto EnableWaitTimeFlag = 1U << 1;
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static constexpr auto RequestC1State = 0U;
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// monitor_var should be aligned to a cache line.
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// monitor_var should be aligned to a cache line.
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alignas(64) u64 monitor_var{};
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alignas(64) u64 monitor_var{};
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_mm_monitorx(&monitor_var, 0, 0);
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_mm_monitorx(&monitor_var, 0, 0);
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_mm_mwaitx(/* extensions*/ 2, /* hints */ 0, /* cycles */ PauseCycles);
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_mm_mwaitx(EnableWaitTimeFlag, RequestC1State, PauseCycles);
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}
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}
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#else
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#else
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static void TPAUSE() {
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static void TPAUSE() {
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static constexpr auto RequestC02State = 0U;
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const auto tsc = FencedRDTSC() + PauseCycles;
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const auto tsc = FencedRDTSC() + PauseCycles;
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const auto eax = static_cast<u32>(tsc & 0xFFFFFFFF);
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const auto eax = static_cast<u32>(tsc & 0xFFFFFFFF);
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const auto edx = static_cast<u32>(tsc >> 32);
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const auto edx = static_cast<u32>(tsc >> 32);
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asm volatile("tpause %0" : : "r"(0), "d"(edx), "a"(eax));
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asm volatile("tpause %0" : : "r"(RequestC02State), "d"(edx), "a"(eax));
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}
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}
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#endif
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#endif
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