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Merge pull request #766 from bunnei/shader-sel
gl_shader_decompiler: Implement SEL instruction.
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commit
2d563ec8d5
@ -288,6 +288,11 @@ union Instruction {
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BitField<49, 1, u64> negate_a;
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} alu_integer;
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union {
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BitField<39, 3, u64> pred;
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BitField<42, 1, u64> neg_pred;
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} sel;
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union {
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BitField<39, 3, u64> pred;
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BitField<42, 1, u64> negate_pred;
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@ -513,6 +518,9 @@ public:
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ISCADD_C, // Scale and Add
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ISCADD_R,
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ISCADD_IMM,
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SEL_C,
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SEL_R,
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SEL_IMM,
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MUFU, // Multi-Function Operator
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RRO_C, // Range Reduction Operator
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RRO_R,
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@ -713,6 +721,9 @@ private:
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INST("0100110000011---", Id::ISCADD_C, Type::ArithmeticInteger, "ISCADD_C"),
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INST("0101110000011---", Id::ISCADD_R, Type::ArithmeticInteger, "ISCADD_R"),
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INST("0011100-00011---", Id::ISCADD_IMM, Type::ArithmeticInteger, "ISCADD_IMM"),
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INST("0100110010100---", Id::SEL_C, Type::ArithmeticInteger, "SEL_C"),
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INST("0101110010100---", Id::SEL_R, Type::ArithmeticInteger, "SEL_R"),
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INST("0011100010100---", Id::SEL_IMM, Type::ArithmeticInteger, "SEL_IMM"),
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INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
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INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"),
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INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"),
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@ -1139,6 +1139,15 @@ private:
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"((" + op_a + " << " + shift + ") + " + op_b + ')', 1, 1);
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break;
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}
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case OpCode::Id::SEL_C:
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case OpCode::Id::SEL_R:
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case OpCode::Id::SEL_IMM: {
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std::string condition =
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GetPredicateCondition(instr.sel.pred, instr.sel.neg_pred != 0);
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regs.SetRegisterToInteger(instr.gpr0, true, 0,
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'(' + condition + ") ? " + op_a + " : " + op_b, 1, 1);
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break;
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}
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case OpCode::Id::LOP_C:
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case OpCode::Id::LOP_R:
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case OpCode::Id::LOP_IMM: {
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