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Merge pull request #2348 from FernandoS27/guest-bindless
Implement Bindless Textures on Shader Decompiler and GL backend
This commit is contained in:
bunnei
GitHub
commit
5bd5140bde
@ -482,19 +482,8 @@ std::vector<Texture::FullTextureInfo> Maxwell3D::GetStageTextures(Regs::ShaderSt
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return textures;
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}
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Texture::FullTextureInfo Maxwell3D::GetStageTexture(Regs::ShaderStage stage,
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Texture::FullTextureInfo Maxwell3D::GetTextureInfo(const Texture::TextureHandle tex_handle,
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std::size_t offset) const {
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auto& shader = state.shader_stages[static_cast<std::size_t>(stage)];
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auto& tex_info_buffer = shader.const_buffers[regs.tex_cb_index];
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ASSERT(tex_info_buffer.enabled && tex_info_buffer.address != 0);
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const GPUVAddr tex_info_address =
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tex_info_buffer.address + offset * sizeof(Texture::TextureHandle);
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ASSERT(tex_info_address < tex_info_buffer.address + tex_info_buffer.size);
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const Texture::TextureHandle tex_handle{memory_manager.Read<u32>(tex_info_address)};
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Texture::FullTextureInfo tex_info{};
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tex_info.index = static_cast<u32>(offset);
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@ -511,6 +500,22 @@ Texture::FullTextureInfo Maxwell3D::GetStageTexture(Regs::ShaderStage stage,
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return tex_info;
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}
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Texture::FullTextureInfo Maxwell3D::GetStageTexture(Regs::ShaderStage stage,
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std::size_t offset) const {
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const auto& shader = state.shader_stages[static_cast<std::size_t>(stage)];
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const auto& tex_info_buffer = shader.const_buffers[regs.tex_cb_index];
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ASSERT(tex_info_buffer.enabled && tex_info_buffer.address != 0);
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const GPUVAddr tex_info_address =
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tex_info_buffer.address + offset * sizeof(Texture::TextureHandle);
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ASSERT(tex_info_address < tex_info_buffer.address + tex_info_buffer.size);
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const Texture::TextureHandle tex_handle{memory_manager.Read<u32>(tex_info_address)};
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return GetTextureInfo(tex_handle, offset);
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}
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u32 Maxwell3D::GetRegisterValue(u32 method) const {
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ASSERT_MSG(method < Regs::NUM_REGS, "Invalid Maxwell3D register");
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return regs.reg_array[method];
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@ -524,4 +529,12 @@ void Maxwell3D::ProcessClearBuffers() {
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rasterizer.Clear();
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}
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u32 Maxwell3D::AccessConstBuffer32(Regs::ShaderStage stage, u64 const_buffer, u64 offset) const {
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const auto& shader_stage = state.shader_stages[static_cast<std::size_t>(stage)];
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const auto& buffer = shader_stage.const_buffers[const_buffer];
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u32 result;
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std::memcpy(&result, memory_manager.GetPointer(buffer.address + offset), sizeof(u32));
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return result;
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}
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} // namespace Tegra::Engines
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@ -1131,12 +1131,18 @@ public:
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/// Write the value to the register identified by method.
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void CallMethod(const GPU::MethodCall& method_call);
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/// Given a Texture Handle, returns the TSC and TIC entries.
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Texture::FullTextureInfo GetTextureInfo(const Texture::TextureHandle tex_handle,
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std::size_t offset) const;
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/// Returns a list of enabled textures for the specified shader stage.
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std::vector<Texture::FullTextureInfo> GetStageTextures(Regs::ShaderStage stage) const;
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/// Returns the texture information for a specific texture in a specific shader stage.
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Texture::FullTextureInfo GetStageTexture(Regs::ShaderStage stage, std::size_t offset) const;
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u32 AccessConstBuffer32(Regs::ShaderStage stage, u64 const_buffer, u64 offset) const;
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/// Memory for macro code - it's undetermined how big this is, however 1MB is much larger than
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/// we've seen used.
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using MacroMemory = std::array<u32, 0x40000>;
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@ -986,6 +986,38 @@ union Instruction {
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}
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} tex;
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union {
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BitField<28, 1, u64> array;
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BitField<29, 2, TextureType> texture_type;
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BitField<31, 4, u64> component_mask;
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BitField<49, 1, u64> nodep_flag;
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BitField<50, 1, u64> dc_flag;
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BitField<36, 1, u64> aoffi_flag;
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BitField<37, 3, TextureProcessMode> process_mode;
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bool IsComponentEnabled(std::size_t component) const {
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return ((1ULL << component) & component_mask) != 0;
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}
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TextureProcessMode GetTextureProcessMode() const {
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return process_mode;
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}
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bool UsesMiscMode(TextureMiscMode mode) const {
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switch (mode) {
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case TextureMiscMode::DC:
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return dc_flag != 0;
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case TextureMiscMode::NODEP:
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return nodep_flag != 0;
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case TextureMiscMode::AOFFI:
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return aoffi_flag != 0;
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default:
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break;
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}
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return false;
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}
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} tex_b;
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union {
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BitField<22, 6, TextureQueryType> query_type;
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BitField<31, 4, u64> component_mask;
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@ -1332,7 +1364,9 @@ public:
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LDG, // Load from global memory
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STG, // Store in global memory
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TEX,
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TEX_B, // Texture Load Bindless
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TXQ, // Texture Query
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TXQ_B, // Texture Query Bindless
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TEXS, // Texture Fetch with scalar/non-vec4 source/destinations
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TLDS, // Texture Load with scalar/non-vec4 source/destinations
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TLD4, // Texture Load 4
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@ -1600,7 +1634,9 @@ private:
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INST("1110111011010---", Id::LDG, Type::Memory, "LDG"),
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INST("1110111011011---", Id::STG, Type::Memory, "STG"),
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INST("110000----111---", Id::TEX, Type::Texture, "TEX"),
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INST("1101111010111---", Id::TEX_B, Type::Texture, "TEX_B"),
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INST("1101111101001---", Id::TXQ, Type::Texture, "TXQ"),
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INST("1101111101010---", Id::TXQ_B, Type::Texture, "TXQ_B"),
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INST("1101-00---------", Id::TEXS, Type::Texture, "TEXS"),
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INST("1101101---------", Id::TLDS, Type::Texture, "TLDS"),
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INST("110010----111---", Id::TLD4, Type::Texture, "TLD4"),
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@ -974,7 +974,15 @@ void RasterizerOpenGL::SetupTextures(Maxwell::ShaderStage stage, const Shader& s
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for (u32 bindpoint = 0; bindpoint < entries.size(); ++bindpoint) {
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const auto& entry = entries[bindpoint];
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const auto texture = maxwell3d.GetStageTexture(stage, entry.GetOffset());
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Tegra::Texture::FullTextureInfo texture;
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if (entry.IsBindless()) {
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const auto cbuf = entry.GetBindlessCBuf();
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Tegra::Texture::TextureHandle tex_handle;
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tex_handle.raw = maxwell3d.AccessConstBuffer32(stage, cbuf.first, cbuf.second);
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texture = maxwell3d.GetTextureInfo(tex_handle, entry.GetOffset());
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} else {
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texture = maxwell3d.GetStageTexture(stage, entry.GetOffset());
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}
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const u32 current_bindpoint = base_bindings.sampler + bindpoint;
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texture_samplers[current_bindpoint].SyncWithConfig(texture.tsc);
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@ -69,6 +69,7 @@ private:
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struct ShaderEntries {
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std::vector<ConstBufferEntry> const_buffers;
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std::vector<SamplerEntry> samplers;
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std::vector<SamplerEntry> bindless_samplers;
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std::vector<GlobalMemoryEntry> global_memory_entries;
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std::array<bool, Maxwell::NumClipDistances> clip_distances{};
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std::size_t shader_length{};
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@ -319,16 +319,19 @@ std::optional<ShaderDiskCacheDecompiled> ShaderDiskCacheOpenGL::LoadDecompiledEn
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u32 type{};
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u8 is_array{};
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u8 is_shadow{};
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u8 is_bindless{};
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if (file.ReadBytes(&offset, sizeof(u64)) != sizeof(u64) ||
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file.ReadBytes(&index, sizeof(u64)) != sizeof(u64) ||
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file.ReadBytes(&type, sizeof(u32)) != sizeof(u32) ||
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file.ReadBytes(&is_array, sizeof(u8)) != sizeof(u8) ||
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file.ReadBytes(&is_shadow, sizeof(u8)) != sizeof(u8)) {
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file.ReadBytes(&is_shadow, sizeof(u8)) != sizeof(u8) ||
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file.ReadBytes(&is_bindless, sizeof(u8)) != sizeof(u8)) {
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return {};
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}
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entry.entries.samplers.emplace_back(
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static_cast<std::size_t>(offset), static_cast<std::size_t>(index),
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static_cast<Tegra::Shader::TextureType>(type), is_array != 0, is_shadow != 0);
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entry.entries.samplers.emplace_back(static_cast<std::size_t>(offset),
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static_cast<std::size_t>(index),
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static_cast<Tegra::Shader::TextureType>(type),
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is_array != 0, is_shadow != 0, is_bindless != 0);
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}
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u32 global_memory_count{};
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@ -393,7 +396,8 @@ bool ShaderDiskCacheOpenGL::SaveDecompiledFile(FileUtil::IOFile& file, u64 uniqu
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file.WriteObject(static_cast<u64>(sampler.GetIndex())) != 1 ||
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file.WriteObject(static_cast<u32>(sampler.GetType())) != 1 ||
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file.WriteObject(static_cast<u8>(sampler.IsArray() ? 1 : 0)) != 1 ||
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file.WriteObject(static_cast<u8>(sampler.IsShadow() ? 1 : 0)) != 1) {
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file.WriteObject(static_cast<u8>(sampler.IsShadow() ? 1 : 0)) != 1 ||
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file.WriteObject(static_cast<u8>(sampler.IsBindless() ? 1 : 0)) != 1) {
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return false;
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}
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}
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@ -40,7 +40,7 @@ static std::size_t GetCoordCount(TextureType texture_type) {
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u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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bool is_bindless = false;
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switch (opcode->get().GetId()) {
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case OpCode::Id::TEX: {
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if (instr.tex.UsesMiscMode(TextureMiscMode::NODEP)) {
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@ -54,7 +54,25 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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const auto process_mode = instr.tex.GetTextureProcessMode();
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WriteTexInstructionFloat(
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bb, instr,
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GetTexCode(instr, texture_type, process_mode, depth_compare, is_array, is_aoffi));
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GetTexCode(instr, texture_type, process_mode, depth_compare, is_array, is_aoffi, {}));
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break;
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}
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case OpCode::Id::TEX_B: {
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UNIMPLEMENTED_IF_MSG(instr.tex.UsesMiscMode(TextureMiscMode::AOFFI),
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"AOFFI is not implemented");
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if (instr.tex.UsesMiscMode(TextureMiscMode::NODEP)) {
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LOG_WARNING(HW_GPU, "TEX.NODEP implementation is incomplete");
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}
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const TextureType texture_type{instr.tex_b.texture_type};
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const bool is_array = instr.tex_b.array != 0;
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const bool is_aoffi = instr.tex.UsesMiscMode(TextureMiscMode::AOFFI);
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const bool depth_compare = instr.tex_b.UsesMiscMode(TextureMiscMode::DC);
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const auto process_mode = instr.tex_b.GetTextureProcessMode();
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WriteTexInstructionFloat(bb, instr,
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GetTexCode(instr, texture_type, process_mode, depth_compare,
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is_array, is_aoffi, {instr.gpr20}));
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break;
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}
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case OpCode::Id::TEXS: {
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@ -134,6 +152,9 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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WriteTexsInstructionFloat(bb, instr, values);
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break;
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}
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case OpCode::Id::TXQ_B:
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is_bindless = true;
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[[fallthrough]];
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case OpCode::Id::TXQ: {
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if (instr.txq.UsesMiscMode(TextureMiscMode::NODEP)) {
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LOG_WARNING(HW_GPU, "TXQ.NODEP implementation is incomplete");
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@ -143,7 +164,10 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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// Sadly, not all texture instructions specify the type of texture their sampler
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// uses. This must be fixed at a later instance.
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const auto& sampler =
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GetSampler(instr.sampler, Tegra::Shader::TextureType::Texture2D, false, false);
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is_bindless
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? GetBindlessSampler(instr.gpr8, Tegra::Shader::TextureType::Texture2D, false,
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false)
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: GetSampler(instr.sampler, Tegra::Shader::TextureType::Texture2D, false, false);
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u32 indexer = 0;
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switch (instr.txq.query_type) {
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@ -154,7 +178,8 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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}
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MetaTexture meta{sampler, {}, {}, {}, {}, {}, {}, element};
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const Node value =
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Operation(OperationCode::TextureQueryDimensions, meta, GetRegister(instr.gpr8));
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Operation(OperationCode::TextureQueryDimensions, meta,
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GetRegister(instr.gpr8.Value() + (is_bindless ? 1 : 0)));
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SetTemporal(bb, indexer++, value);
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}
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for (u32 i = 0; i < indexer; ++i) {
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@ -168,6 +193,9 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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}
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break;
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}
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case OpCode::Id::TMML_B:
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is_bindless = true;
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[[fallthrough]];
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case OpCode::Id::TMML: {
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UNIMPLEMENTED_IF_MSG(instr.tmml.UsesMiscMode(Tegra::Shader::TextureMiscMode::NDV),
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"NDV is not implemented");
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@ -178,7 +206,9 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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auto texture_type = instr.tmml.texture_type.Value();
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const bool is_array = instr.tmml.array != 0;
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const auto& sampler = GetSampler(instr.sampler, texture_type, is_array, false);
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const auto& sampler = is_bindless
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? GetBindlessSampler(instr.gpr20, texture_type, is_array, false)
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: GetSampler(instr.sampler, texture_type, is_array, false);
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std::vector<Node> coords;
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@ -199,17 +229,19 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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coords.push_back(GetRegister(instr.gpr8.Value() + 1));
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texture_type = TextureType::Texture2D;
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}
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u32 indexer = 0;
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for (u32 element = 0; element < 2; ++element) {
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if (!instr.tmml.IsComponentEnabled(element)) {
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continue;
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}
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auto params = coords;
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MetaTexture meta{sampler, {}, {}, {}, {}, {}, {}, element};
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const Node value = Operation(OperationCode::TextureQueryLod, meta, std::move(params));
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SetTemporal(bb, element, value);
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SetTemporal(bb, indexer++, value);
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}
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for (u32 element = 0; element < 2; ++element) {
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SetRegister(bb, instr.gpr0.Value() + element, GetTemporal(element));
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for (u32 i = 0; i < indexer; ++i) {
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SetRegister(bb, instr.gpr0.Value() + i, GetTemporal(i));
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}
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break;
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}
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case OpCode::Id::TLDS: {
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@ -254,6 +286,34 @@ const Sampler& ShaderIR::GetSampler(const Tegra::Shader::Sampler& sampler, Textu
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return *used_samplers.emplace(entry).first;
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}
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const Sampler& ShaderIR::GetBindlessSampler(const Tegra::Shader::Register& reg, TextureType type,
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bool is_array, bool is_shadow) {
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const Node sampler_register = GetRegister(reg);
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const Node base_sampler =
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TrackCbuf(sampler_register, global_code, static_cast<s64>(global_code.size()));
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const auto cbuf = std::get_if<CbufNode>(base_sampler);
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const auto cbuf_offset_imm = std::get_if<ImmediateNode>(cbuf->GetOffset());
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ASSERT(cbuf_offset_imm != nullptr);
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const auto cbuf_offset = cbuf_offset_imm->GetValue();
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const auto cbuf_index = cbuf->GetIndex();
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const u64 cbuf_key = (cbuf_index << 32) | cbuf_offset;
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// If this sampler has already been used, return the existing mapping.
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const auto itr =
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std::find_if(used_samplers.begin(), used_samplers.end(),
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[&](const Sampler& entry) { return entry.GetOffset() == cbuf_key; });
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if (itr != used_samplers.end()) {
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ASSERT(itr->GetType() == type && itr->IsArray() == is_array &&
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itr->IsShadow() == is_shadow);
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return *itr;
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}
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// Otherwise create a new mapping for this sampler
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const std::size_t next_index = used_samplers.size();
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const Sampler entry{cbuf_index, cbuf_offset, next_index, type, is_array, is_shadow};
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return *used_samplers.emplace(entry).first;
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}
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void ShaderIR::WriteTexInstructionFloat(NodeBlock& bb, Instruction instr, const Node4& components) {
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u32 dest_elem = 0;
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for (u32 elem = 0; elem < 4; ++elem) {
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@ -326,22 +386,27 @@ void ShaderIR::WriteTexsInstructionHalfFloat(NodeBlock& bb, Instruction instr,
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Node4 ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type,
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TextureProcessMode process_mode, std::vector<Node> coords,
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Node array, Node depth_compare, u32 bias_offset,
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std::vector<Node> aoffi) {
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std::vector<Node> aoffi,
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std::optional<Tegra::Shader::Register> bindless_reg) {
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const bool is_array = array;
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const bool is_shadow = depth_compare;
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const bool is_bindless = bindless_reg.has_value();
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UNIMPLEMENTED_IF_MSG((texture_type == TextureType::Texture3D && (is_array || is_shadow)) ||
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(texture_type == TextureType::TextureCube && is_array && is_shadow),
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"This method is not supported.");
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const auto& sampler = GetSampler(instr.sampler, texture_type, is_array, is_shadow);
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const auto& sampler = is_bindless
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? GetBindlessSampler(*bindless_reg, texture_type, is_array, is_shadow)
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: GetSampler(instr.sampler, texture_type, is_array, is_shadow);
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const bool lod_needed = process_mode == TextureProcessMode::LZ ||
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process_mode == TextureProcessMode::LL ||
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process_mode == TextureProcessMode::LLA;
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// LOD selection (either via bias or explicit textureLod) not supported in GL for
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// sampler2DArrayShadow and samplerCubeArrayShadow.
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// LOD selection (either via bias or explicit textureLod) not
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// supported in GL for sampler2DArrayShadow and
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// samplerCubeArrayShadow.
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const bool gl_lod_supported =
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!((texture_type == Tegra::Shader::TextureType::Texture2D && is_array && is_shadow) ||
|
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(texture_type == Tegra::Shader::TextureType::TextureCube && is_array && is_shadow));
|
||||
@ -359,8 +424,9 @@ Node4 ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type,
|
||||
lod = Immediate(0.0f);
|
||||
break;
|
||||
case TextureProcessMode::LB:
|
||||
// If present, lod or bias are always stored in the register indexed by the gpr20
|
||||
// field with an offset depending on the usage of the other registers
|
||||
// If present, lod or bias are always stored in the register
|
||||
// indexed by the gpr20 field with an offset depending on the
|
||||
// usage of the other registers
|
||||
bias = GetRegister(instr.gpr20.Value() + bias_offset);
|
||||
break;
|
||||
case TextureProcessMode::LL:
|
||||
@ -384,11 +450,18 @@ Node4 ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type,
|
||||
|
||||
Node4 ShaderIR::GetTexCode(Instruction instr, TextureType texture_type,
|
||||
TextureProcessMode process_mode, bool depth_compare, bool is_array,
|
||||
bool is_aoffi) {
|
||||
bool is_aoffi, std::optional<Tegra::Shader::Register> bindless_reg) {
|
||||
const bool lod_bias_enabled{
|
||||
(process_mode != TextureProcessMode::None && process_mode != TextureProcessMode::LZ)};
|
||||
|
||||
const bool is_bindless = bindless_reg.has_value();
|
||||
|
||||
u64 parameter_register = instr.gpr20.Value();
|
||||
if (is_bindless) {
|
||||
++parameter_register;
|
||||
}
|
||||
|
||||
const u32 bias_lod_offset = (is_bindless ? 1 : 0);
|
||||
if (lod_bias_enabled) {
|
||||
++parameter_register;
|
||||
}
|
||||
@ -423,7 +496,8 @@ Node4 ShaderIR::GetTexCode(Instruction instr, TextureType texture_type,
|
||||
dc = GetRegister(parameter_register++);
|
||||
}
|
||||
|
||||
return GetTextureCode(instr, texture_type, process_mode, coords, array, dc, 0, aoffi);
|
||||
return GetTextureCode(instr, texture_type, process_mode, coords, array, dc, bias_lod_offset,
|
||||
aoffi, bindless_reg);
|
||||
}
|
||||
|
||||
Node4 ShaderIR::GetTexsCode(Instruction instr, TextureType texture_type,
|
||||
@ -459,7 +533,8 @@ Node4 ShaderIR::GetTexsCode(Instruction instr, TextureType texture_type,
|
||||
dc = GetRegister(depth_register);
|
||||
}
|
||||
|
||||
return GetTextureCode(instr, texture_type, process_mode, coords, array, dc, bias_offset, {});
|
||||
return GetTextureCode(instr, texture_type, process_mode, coords, array, dc, bias_offset, {},
|
||||
{});
|
||||
}
|
||||
|
||||
Node4 ShaderIR::GetTld4Code(Instruction instr, TextureType texture_type, bool depth_compare,
|
||||
|
||||
@ -196,9 +196,23 @@ enum class ExitMethod {
|
||||
|
||||
class Sampler {
|
||||
public:
|
||||
// Use this constructor for bounded Samplers
|
||||
explicit Sampler(std::size_t offset, std::size_t index, Tegra::Shader::TextureType type,
|
||||
bool is_array, bool is_shadow)
|
||||
: offset{offset}, index{index}, type{type}, is_array{is_array}, is_shadow{is_shadow} {}
|
||||
: offset{offset}, index{index}, type{type}, is_array{is_array}, is_shadow{is_shadow},
|
||||
is_bindless{false} {}
|
||||
|
||||
// Use this constructor for bindless Samplers
|
||||
explicit Sampler(u32 cbuf_index, u32 cbuf_offset, std::size_t index,
|
||||
Tegra::Shader::TextureType type, bool is_array, bool is_shadow)
|
||||
: offset{(static_cast<u64>(cbuf_index) << 32) | cbuf_offset}, index{index}, type{type},
|
||||
is_array{is_array}, is_shadow{is_shadow}, is_bindless{true} {}
|
||||
|
||||
// Use this only for serialization/deserialization
|
||||
explicit Sampler(std::size_t offset, std::size_t index, Tegra::Shader::TextureType type,
|
||||
bool is_array, bool is_shadow, bool is_bindless)
|
||||
: offset{offset}, index{index}, type{type}, is_array{is_array}, is_shadow{is_shadow},
|
||||
is_bindless{is_bindless} {}
|
||||
|
||||
std::size_t GetOffset() const {
|
||||
return offset;
|
||||
@ -220,6 +234,14 @@ public:
|
||||
return is_shadow;
|
||||
}
|
||||
|
||||
bool IsBindless() const {
|
||||
return is_bindless;
|
||||
}
|
||||
|
||||
std::pair<u32, u32> GetBindlessCBuf() const {
|
||||
return {static_cast<u32>(offset >> 32), static_cast<u32>(offset)};
|
||||
}
|
||||
|
||||
bool operator<(const Sampler& rhs) const {
|
||||
return std::tie(offset, index, type, is_array, is_shadow) <
|
||||
std::tie(rhs.offset, rhs.index, rhs.type, rhs.is_array, rhs.is_shadow);
|
||||
@ -233,6 +255,7 @@ private:
|
||||
Tegra::Shader::TextureType type{}; ///< The type used to sample this texture (Texture2D, etc)
|
||||
bool is_array{}; ///< Whether the texture is being sampled as an array texture or not.
|
||||
bool is_shadow{}; ///< Whether the texture is being sampled as a depth texture or not.
|
||||
bool is_bindless{}; ///< Whether this sampler belongs to a bindless texture or not.
|
||||
};
|
||||
|
||||
class ConstBuffer {
|
||||
@ -735,6 +758,11 @@ private:
|
||||
const Sampler& GetSampler(const Tegra::Shader::Sampler& sampler,
|
||||
Tegra::Shader::TextureType type, bool is_array, bool is_shadow);
|
||||
|
||||
// Accesses a texture sampler for a bindless texture.
|
||||
const Sampler& GetBindlessSampler(const Tegra::Shader::Register& reg,
|
||||
Tegra::Shader::TextureType type, bool is_array,
|
||||
bool is_shadow);
|
||||
|
||||
/// Extracts a sequence of bits from a node
|
||||
Node BitfieldExtract(Node value, u32 offset, u32 bits);
|
||||
|
||||
@ -748,7 +776,8 @@ private:
|
||||
|
||||
Node4 GetTexCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
|
||||
Tegra::Shader::TextureProcessMode process_mode, bool depth_compare,
|
||||
bool is_array, bool is_aoffi);
|
||||
bool is_array, bool is_aoffi,
|
||||
std::optional<Tegra::Shader::Register> bindless_reg);
|
||||
|
||||
Node4 GetTexsCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
|
||||
Tegra::Shader::TextureProcessMode process_mode, bool depth_compare,
|
||||
@ -768,7 +797,8 @@ private:
|
||||
|
||||
Node4 GetTextureCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
|
||||
Tegra::Shader::TextureProcessMode process_mode, std::vector<Node> coords,
|
||||
Node array, Node depth_compare, u32 bias_offset, std::vector<Node> aoffi);
|
||||
Node array, Node depth_compare, u32 bias_offset, std::vector<Node> aoffi,
|
||||
std::optional<Tegra::Shader::Register> bindless_reg);
|
||||
|
||||
Node GetVideoOperand(Node op, bool is_chunk, bool is_signed, Tegra::Shader::VideoType type,
|
||||
u64 byte_height);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user