mirror of
https://github.com/yuzu-emu/yuzu-mainline.git
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Merge pull request #2695 from JayFoxRox/gs-regs
Prepare Pica registers for Geometry Shaders
This commit is contained in:
Weiyi Wang
GitHub
commit
9bd3986540
@ -32,12 +32,13 @@ namespace Pica {
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namespace CommandProcessor {
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static int float_regs_counter = 0;
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static int vs_float_regs_counter = 0;
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static u32 vs_uniform_write_buffer[4];
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static u32 uniform_write_buffer[4];
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static int gs_float_regs_counter = 0;
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static u32 gs_uniform_write_buffer[4];
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static int default_attr_counter = 0;
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static u32 default_attr_write_buffer[3];
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// Expand a 4-bit mask to 4-byte mask, e.g. 0b0101 -> 0x00FF00FF
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@ -48,6 +49,97 @@ static const u32 expand_bits_to_bytes[] = {
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MICROPROFILE_DEFINE(GPU_Drawing, "GPU", "Drawing", MP_RGB(50, 50, 240));
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static const char* GetShaderSetupTypeName(Shader::ShaderSetup& setup) {
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if (&setup == &g_state.vs) {
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return "vertex shader";
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}
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if (&setup == &g_state.gs) {
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return "geometry shader";
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}
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return "unknown shader";
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}
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static void WriteUniformBoolReg(Shader::ShaderSetup& setup, u32 value) {
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for (unsigned i = 0; i < setup.uniforms.b.size(); ++i)
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setup.uniforms.b[i] = (value & (1 << i)) != 0;
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}
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static void WriteUniformIntReg(Shader::ShaderSetup& setup, unsigned index,
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const Math::Vec4<u8>& values) {
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ASSERT(index < setup.uniforms.i.size());
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setup.uniforms.i[index] = values;
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LOG_TRACE(HW_GPU, "Set %s integer uniform %d to %02x %02x %02x %02x",
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GetShaderSetupTypeName(setup), index, values.x, values.y, values.z, values.w);
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}
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static void WriteUniformFloatReg(ShaderRegs& config, Shader::ShaderSetup& setup,
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int& float_regs_counter, u32 uniform_write_buffer[4], u32 value) {
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auto& uniform_setup = config.uniform_setup;
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// TODO: Does actual hardware indeed keep an intermediate buffer or does
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// it directly write the values?
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uniform_write_buffer[float_regs_counter++] = value;
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// Uniforms are written in a packed format such that four float24 values are encoded in
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// three 32-bit numbers. We write to internal memory once a full such vector is
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// written.
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if ((float_regs_counter >= 4 && uniform_setup.IsFloat32()) ||
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(float_regs_counter >= 3 && !uniform_setup.IsFloat32())) {
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float_regs_counter = 0;
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auto& uniform = setup.uniforms.f[uniform_setup.index];
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if (uniform_setup.index >= 96) {
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LOG_ERROR(HW_GPU, "Invalid %s float uniform index %d", GetShaderSetupTypeName(setup),
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(int)uniform_setup.index);
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} else {
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// NOTE: The destination component order indeed is "backwards"
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if (uniform_setup.IsFloat32()) {
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for (auto i : {0, 1, 2, 3})
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uniform[3 - i] = float24::FromFloat32(*(float*)(&uniform_write_buffer[i]));
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} else {
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// TODO: Untested
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uniform.w = float24::FromRaw(uniform_write_buffer[0] >> 8);
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uniform.z = float24::FromRaw(((uniform_write_buffer[0] & 0xFF) << 16) |
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((uniform_write_buffer[1] >> 16) & 0xFFFF));
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uniform.y = float24::FromRaw(((uniform_write_buffer[1] & 0xFFFF) << 8) |
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((uniform_write_buffer[2] >> 24) & 0xFF));
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uniform.x = float24::FromRaw(uniform_write_buffer[2] & 0xFFFFFF);
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}
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LOG_TRACE(HW_GPU, "Set %s float uniform %x to (%f %f %f %f)",
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GetShaderSetupTypeName(setup), (int)uniform_setup.index,
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uniform.x.ToFloat32(), uniform.y.ToFloat32(), uniform.z.ToFloat32(),
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uniform.w.ToFloat32());
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// TODO: Verify that this actually modifies the register!
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uniform_setup.index.Assign(uniform_setup.index + 1);
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}
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}
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}
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static void WriteProgramCode(ShaderRegs& config, Shader::ShaderSetup& setup,
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unsigned max_program_code_length, u32 value) {
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if (config.program.offset >= max_program_code_length) {
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LOG_ERROR(HW_GPU, "Invalid %s program offset %d", GetShaderSetupTypeName(setup),
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(int)config.program.offset);
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} else {
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setup.program_code[config.program.offset] = value;
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config.program.offset++;
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}
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}
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static void WriteSwizzlePatterns(ShaderRegs& config, Shader::ShaderSetup& setup, u32 value) {
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if (config.swizzle_patterns.offset >= setup.swizzle_data.size()) {
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LOG_ERROR(HW_GPU, "Invalid %s swizzle pattern offset %d", GetShaderSetupTypeName(setup),
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(int)config.swizzle_patterns.offset);
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} else {
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setup.swizzle_data[config.swizzle_patterns.offset] = value;
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config.swizzle_patterns.offset++;
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}
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}
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static void WritePicaReg(u32 id, u32 value, u32 mask) {
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auto& regs = g_state.regs;
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@ -330,21 +422,70 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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break;
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}
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case PICA_REG_INDEX(vs.bool_uniforms):
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for (unsigned i = 0; i < 16; ++i)
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g_state.vs.uniforms.b[i] = (regs.vs.bool_uniforms.Value() & (1 << i)) != 0;
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case PICA_REG_INDEX(gs.bool_uniforms):
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WriteUniformBoolReg(g_state.gs, value);
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break;
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case PICA_REG_INDEX_WORKAROUND(gs.int_uniforms[0], 0x281):
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case PICA_REG_INDEX_WORKAROUND(gs.int_uniforms[1], 0x282):
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case PICA_REG_INDEX_WORKAROUND(gs.int_uniforms[2], 0x283):
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case PICA_REG_INDEX_WORKAROUND(gs.int_uniforms[3], 0x284): {
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unsigned index = (id - PICA_REG_INDEX_WORKAROUND(gs.int_uniforms[0], 0x281));
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auto values = regs.gs.int_uniforms[index];
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WriteUniformIntReg(g_state.gs, index,
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Math::Vec4<u8>(values.x, values.y, values.z, values.w));
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break;
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}
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case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[0], 0x291):
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case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[1], 0x292):
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case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[2], 0x293):
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case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[3], 0x294):
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case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[4], 0x295):
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case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[5], 0x296):
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case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[6], 0x297):
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case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[7], 0x298): {
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WriteUniformFloatReg(g_state.regs.gs, g_state.gs, gs_float_regs_counter,
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gs_uniform_write_buffer, value);
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break;
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}
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case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[0], 0x29c):
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case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[1], 0x29d):
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case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[2], 0x29e):
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case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[3], 0x29f):
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case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[4], 0x2a0):
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case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[5], 0x2a1):
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case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[6], 0x2a2):
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case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[7], 0x2a3): {
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WriteProgramCode(g_state.regs.gs, g_state.gs, 4096, value);
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break;
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}
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case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[0], 0x2a6):
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case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[1], 0x2a7):
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case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[2], 0x2a8):
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case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[3], 0x2a9):
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case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[4], 0x2aa):
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case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[5], 0x2ab):
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case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[6], 0x2ac):
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case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[7], 0x2ad): {
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WriteSwizzlePatterns(g_state.regs.gs, g_state.gs, value);
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break;
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}
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case PICA_REG_INDEX(vs.bool_uniforms):
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WriteUniformBoolReg(g_state.vs, value);
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break;
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case PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[0], 0x2b1):
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case PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[1], 0x2b2):
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case PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[2], 0x2b3):
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case PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[3], 0x2b4): {
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int index = (id - PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[0], 0x2b1));
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unsigned index = (id - PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[0], 0x2b1));
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auto values = regs.vs.int_uniforms[index];
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g_state.vs.uniforms.i[index] = Math::Vec4<u8>(values.x, values.y, values.z, values.w);
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LOG_TRACE(HW_GPU, "Set integer uniform %d to %02x %02x %02x %02x", index, values.x.Value(),
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values.y.Value(), values.z.Value(), values.w.Value());
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WriteUniformIntReg(g_state.vs, index,
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Math::Vec4<u8>(values.x, values.y, values.z, values.w));
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break;
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}
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@ -356,51 +497,11 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[5], 0x2c6):
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case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[6], 0x2c7):
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case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[7], 0x2c8): {
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auto& uniform_setup = regs.vs.uniform_setup;
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// TODO: Does actual hardware indeed keep an intermediate buffer or does
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// it directly write the values?
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uniform_write_buffer[float_regs_counter++] = value;
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// Uniforms are written in a packed format such that four float24 values are encoded in
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// three 32-bit numbers. We write to internal memory once a full such vector is
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// written.
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if ((float_regs_counter >= 4 && uniform_setup.IsFloat32()) ||
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(float_regs_counter >= 3 && !uniform_setup.IsFloat32())) {
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float_regs_counter = 0;
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auto& uniform = g_state.vs.uniforms.f[uniform_setup.index];
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if (uniform_setup.index > 95) {
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LOG_ERROR(HW_GPU, "Invalid VS uniform index %d", (int)uniform_setup.index);
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break;
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}
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// NOTE: The destination component order indeed is "backwards"
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if (uniform_setup.IsFloat32()) {
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for (auto i : {0, 1, 2, 3})
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uniform[3 - i] = float24::FromFloat32(*(float*)(&uniform_write_buffer[i]));
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} else {
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// TODO: Untested
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uniform.w = float24::FromRaw(uniform_write_buffer[0] >> 8);
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uniform.z = float24::FromRaw(((uniform_write_buffer[0] & 0xFF) << 16) |
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((uniform_write_buffer[1] >> 16) & 0xFFFF));
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uniform.y = float24::FromRaw(((uniform_write_buffer[1] & 0xFFFF) << 8) |
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((uniform_write_buffer[2] >> 24) & 0xFF));
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uniform.x = float24::FromRaw(uniform_write_buffer[2] & 0xFFFFFF);
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}
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LOG_TRACE(HW_GPU, "Set uniform %x to (%f %f %f %f)", (int)uniform_setup.index,
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uniform.x.ToFloat32(), uniform.y.ToFloat32(), uniform.z.ToFloat32(),
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uniform.w.ToFloat32());
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// TODO: Verify that this actually modifies the register!
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uniform_setup.index.Assign(uniform_setup.index + 1);
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}
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WriteUniformFloatReg(g_state.regs.vs, g_state.vs, vs_float_regs_counter,
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vs_uniform_write_buffer, value);
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break;
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}
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// Load shader program code
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case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[0], 0x2cc):
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case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[1], 0x2cd):
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case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[2], 0x2ce):
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@ -409,12 +510,10 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[5], 0x2d1):
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case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[6], 0x2d2):
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case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[7], 0x2d3): {
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g_state.vs.program_code[regs.vs.program.offset] = value;
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regs.vs.program.offset++;
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WriteProgramCode(g_state.regs.vs, g_state.vs, 512, value);
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break;
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}
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// Load swizzle pattern data
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case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[0], 0x2d6):
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case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[1], 0x2d7):
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case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[2], 0x2d8):
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@ -423,8 +522,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[5], 0x2db):
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case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[6], 0x2dc):
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case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[7], 0x2dd): {
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g_state.vs.swizzle_data[regs.vs.swizzle_patterns.offset] = value;
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regs.vs.swizzle_patterns.offset++;
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WriteSwizzlePatterns(g_state.regs.vs, g_state.vs, value);
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break;
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}
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@ -24,6 +24,9 @@ namespace Pica {
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namespace Shader {
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constexpr unsigned MAX_PROGRAM_CODE_LENGTH = 4096;
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constexpr unsigned MAX_SWIZZLE_DATA_LENGTH = 4096;
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struct AttributeBuffer {
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alignas(16) Math::Vec4<float24> attr[16];
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};
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@ -144,8 +147,8 @@ struct ShaderSetup {
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return offsetof(ShaderSetup, uniforms.i) + index * sizeof(Math::Vec4<u8>);
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}
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std::array<u32, 1024> program_code;
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std::array<u32, 1024> swizzle_data;
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std::array<u32, MAX_PROGRAM_CODE_LENGTH> program_code;
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std::array<u32, MAX_SWIZZLE_DATA_LENGTH> swizzle_data;
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/// Data private to ShaderEngines
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struct EngineData {
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@ -653,7 +653,7 @@ static void RunInterpreter(const ShaderSetup& setup, UnitState& state, DebugData
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}
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void InterpreterEngine::SetupBatch(ShaderSetup& setup, unsigned int entry_point) {
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ASSERT(entry_point < 1024);
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ASSERT(entry_point < MAX_PROGRAM_CODE_LENGTH);
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setup.engine_data.entry_point = entry_point;
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}
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@ -15,7 +15,7 @@ JitX64Engine::JitX64Engine() = default;
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JitX64Engine::~JitX64Engine() = default;
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void JitX64Engine::SetupBatch(ShaderSetup& setup, unsigned int entry_point) {
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ASSERT(entry_point < 1024);
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ASSERT(entry_point < MAX_PROGRAM_CODE_LENGTH);
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setup.engine_data.entry_point = entry_point;
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u64 code_hash = Common::ComputeHash64(&setup.program_code, sizeof(setup.program_code));
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@ -834,8 +834,8 @@ void JitShader::FindReturnOffsets() {
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std::sort(return_offsets.begin(), return_offsets.end());
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}
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void JitShader::Compile(const std::array<u32, 1024>* program_code_,
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const std::array<u32, 1024>* swizzle_data_) {
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void JitShader::Compile(const std::array<u32, MAX_PROGRAM_CODE_LENGTH>* program_code_,
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const std::array<u32, MAX_SWIZZLE_DATA_LENGTH>* swizzle_data_) {
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program_code = program_code_;
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swizzle_data = swizzle_data_;
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@ -22,8 +22,8 @@ namespace Pica {
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namespace Shader {
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/// Memory allocated for each compiled shader (64Kb)
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constexpr size_t MAX_SHADER_SIZE = 1024 * 64;
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/// Memory allocated for each compiled shader
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constexpr size_t MAX_SHADER_SIZE = MAX_PROGRAM_CODE_LENGTH * 64;
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/**
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* This class implements the shader JIT compiler. It recompiles a Pica shader program into x86_64
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@ -37,8 +37,8 @@ public:
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program(&setup, &state, instruction_labels[offset].getAddress());
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}
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void Compile(const std::array<u32, 1024>* program_code,
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const std::array<u32, 1024>* swizzle_data);
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void Compile(const std::array<u32, MAX_PROGRAM_CODE_LENGTH>* program_code,
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const std::array<u32, MAX_SWIZZLE_DATA_LENGTH>* swizzle_data);
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void Compile_ADD(Instruction instr);
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void Compile_DP3(Instruction instr);
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@ -104,11 +104,11 @@ private:
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*/
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void FindReturnOffsets();
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const std::array<u32, 1024>* program_code = nullptr;
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const std::array<u32, 1024>* swizzle_data = nullptr;
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const std::array<u32, MAX_PROGRAM_CODE_LENGTH>* program_code = nullptr;
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const std::array<u32, MAX_SWIZZLE_DATA_LENGTH>* swizzle_data = nullptr;
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/// Mapping of Pica VS instructions to pointers in the emitted code
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std::array<Xbyak::Label, 1024> instruction_labels;
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std::array<Xbyak::Label, MAX_PROGRAM_CODE_LENGTH> instruction_labels;
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/// Offsets in code where a return needs to be inserted
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std::vector<unsigned> return_offsets;
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