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https://github.com/yuzu-emu/yuzu-mainline.git
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abc5b3347d
98e2380 fuzz_with_unicorn: Disable testing of FDIV
041b7d5 block_of_code: Add ABI_PARAMS array
2a2371c A64: Implement MLA, MLS (by element), vector single/double variant
78c640a A64: Implement FMLS (vector), single/double variant
b6b6993 emit_x64_vector_floating_point: Specify NanHandler::function_type explicitly
4b9d12a emit_x64_vector_floating_point: ChooseOnFsize arguments maybe_unused
b1e3616 IR: Implement FPVectorNeg
4343612 A64: Implement FMLA (vector), single/double variant
93eeb25 IR: Implement FPVectorMulAdd
57e5c7e emit_x64_vector_floating_point: Standardize naming scheme
bcb9e41 emit_x64_floating_point: Simplify indexers
83aa585 emit_x64_vector_floating_point: Simplify EmitVectorOperation*
f4087c8 mp: rename mp.h to mp/function_info.h
1864090 emit_x64_vector: Slightly improve ArithmeticShiftRightByte
e048441 emit_x64_vector: Simplify VectorShuffleImpl
ff025e8 IR: Implement A64OrQC
6fac68d A64: Implement UQSHRN, UQRSHRN (vector)
5a8d9c3 emit_x64_vector: -0x80000000 isn't -0x80000000
759289e A64: Implement UQXTN (vector)
2a96281 emit_x64_vector: Fix non-SSE4.1 saturated narrowing reconstruction comparison
0682353 A64: Implement SQXTN (vector)
6c5229e emit_x64_vector: packusdw reqiures SSE4.1
158d9b1 A64: Implement SQSHRUN, SQRSHRUN (vector)
f886013 simd_shift_by_immediate: Simplify ShiftRight
d9b59c6 A64: Implement SQXTUN
50fe28b microinstruction: Reorganize FPSCR related instruction queries
d9d036a microinstruction: Add missing FP scalar opcodes to ReadsFromFPSCR() and WritesToFPSCR()
db96163 u128: Make Bit() a const-qualified member function
f7052ae A64: Implement FRSQRTS (vector), single/double variant
0925ef6 A64: Implement FRSQRTE (vector), single/double variant
f4cbbe3 A64: Implement FRSQRTS (scalar), single/double variant
4ef864e IR: Implement FPRSqrtStepFused
9dffeeb fp: Implement FPRSqrtStepFused
aa04556 fp: Implement FPNeg
cbde1c5 process_nan: Add two operand variant
1ec2663 A64: Implement FMAXP, FMINP, FMAXNMP and FMINNMP's scalar double/single-precision variant
027ddf9 emit_x64_floating_point: Fixup special NaN case in FMA FPMulAdd implementation
75a9f77 fp: Use a forward declaration in fused.h
1ee1630 u128: Implement comparison operators in terms of one another
3b77f48 tests: Print cpu info
bed3cc0 u128: StickyLogicalShiftRight requires special-casing for amount == 64
15d04f4 A64: Implement FMLA and FMLS (by element)'s double/single-precision scalar variant
7cfccdf A64: Implement FMUL (by element)'s scalar double/single-precision variant
7d2d62e (fpmuladd) emit_x64_floating_point: Implement accurate fallback for FPMulAdd{32,64}
a599eac fp: Implement FPMulAdd
d70b90e process_nan: Add FPProcessNaNs3
38ef0e0 block_of_code: Add SysV ABI fifth and sixth parameters
8e2ff56 u128: Add StickyLogicalShiftRight
3b337df u128: Add Multiply64To128
8219075 u128: Add u128::Bit
a574dcb u128: Add comparison operators
391d6d4 unpacked: Use ResidualErrorOnRightShift in FPRoundBase
5e0cf9c fp: Remove MantissaT
8c0a84c FPRSqrtEstimate: Improve documentation of RecipSqrtEstimate
c41d855 FPRSqrtEstimate: Deduplicate array bounds
4cf055b A64: Implement FMAXV, FMINV, FMAXNMV, and FMINNMV
bf24f0f FPRSqrtEstimate: Use forward declarations where applicable
206230e translate: Return by bool in helpers where applicable
346b725 Simplify fallback case for EmitVectorSetElement64()
2c34e1d emit_x64_floating_point: s/Esimate/Estimate/
5213fb6 simd_scalar_two_register_misc: Implement FRSQRTE, scalar variant
7ed089f IR: Implement FPRSqrtEstimate
cd2e286 simd_vector_x_indexed_element: Implement FMUL (by element), vector variant
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| .. | ||
| boost@d80e506e17 | ||
| catch@d2a130f243 | ||
| cmake-modules | ||
| dynarmic@98e2380129 | ||
| fmt@c2ce7e4f07 | ||
| getopt | ||
| glad | ||
| inih | ||
| lz4@4db65c1d99 | ||
| microprofile | ||
| unicorn@73f4573535 | ||
| xbyak@71b75f653f | ||
| CMakeLists.txt | ||