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GPU: Added the render target (RT) registers to Maxwell3D's reg structure.

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This commit is contained in:
Subv 2018-03-19 16:46:29 -05:00
parent b2d7c92cae
commit 21d9519032
1 changed files with 32 additions and 1 deletions
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33
src/video_core/engines/maxwell_3d.h
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@ -31,6 +31,7 @@ public:
struct Regs { struct Regs {
static constexpr size_t NUM_REGS = 0xE36; static constexpr size_t NUM_REGS = 0xE36;
static constexpr size_t NumRenderTargets = 8;
static constexpr size_t NumCBData = 16; static constexpr size_t NumCBData = 16;
static constexpr size_t NumVertexArrays = 32; static constexpr size_t NumVertexArrays = 32;
static constexpr size_t MaxShaderProgram = 6; static constexpr size_t MaxShaderProgram = 6;
@ -62,7 +63,35 @@ public:
union { union {
struct { struct {
INSERT_PADDING_WORDS(0x557); INSERT_PADDING_WORDS(0x200);
struct {
u32 address_high;
u32 address_low;
u32 horiz;
u32 vert;
u32 format;
u32 block_dimensions;
u32 array_mode;
u32 layer_stride;
u32 base_layer;
INSERT_PADDING_WORDS(7);
GPUVAddr Address() const {
return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
address_low);
}
} rt[NumRenderTargets];
INSERT_PADDING_WORDS(0x207);
struct {
union {
BitField<0, 4, u32> count;
};
} rt_control;
INSERT_PADDING_WORDS(0xCF);
struct { struct {
u32 tsc_address_high; u32 tsc_address_high;
@ -291,6 +320,8 @@ private:
static_assert(offsetof(Maxwell3D::Regs, field_name) == position * 4, \ static_assert(offsetof(Maxwell3D::Regs, field_name) == position * 4, \
"Field " #field_name " has invalid position") "Field " #field_name " has invalid position")
ASSERT_REG_POSITION(rt, 0x200);
ASSERT_REG_POSITION(rt_control, 0x487);
ASSERT_REG_POSITION(tsc, 0x557); ASSERT_REG_POSITION(tsc, 0x557);
ASSERT_REG_POSITION(tic, 0x55D); ASSERT_REG_POSITION(tic, 0x55D);
ASSERT_REG_POSITION(code_address, 0x582); ASSERT_REG_POSITION(code_address, 0x582);