mirror of
https://github.com/yuzu-emu/yuzu.git
synced 2024-11-28 08:04:25 +01:00
shader: Implement TXD
This commit is contained in:
parent
d5bfc63088
commit
630273b629
@ -133,6 +133,7 @@ add_library(shader_recompiler STATIC
|
||||
frontend/maxwell/translate/impl/texture_fetch_swizzled.cpp
|
||||
frontend/maxwell/translate/impl/texture_gather_swizzled.cpp
|
||||
frontend/maxwell/translate/impl/texture_gather.cpp
|
||||
frontend/maxwell/translate/impl/texture_gradient.cpp
|
||||
frontend/maxwell/translate/impl/texture_load_swizzled.cpp
|
||||
frontend/maxwell/translate/impl/texture_load.cpp
|
||||
frontend/maxwell/translate/impl/texture_mipmap_level.cpp
|
||||
|
@ -261,8 +261,8 @@ INST(TLDS, "TLDS", "1101 -01- ---- ----")
|
||||
INST(TMML, "TMML", "1101 1111 0101 1---")
|
||||
INST(TMML_b, "TMML (b)", "1101 1111 0110 0---")
|
||||
INST(TXA, "TXA", "1101 1111 0100 0---")
|
||||
INST(TXD, "TXD", "1101 1110 0011 10--")
|
||||
INST(TXD_b, "TXD (b)", "1101 1110 0111 10--")
|
||||
INST(TXD, "TXD", "1101 1110 00-- ----")
|
||||
INST(TXD_b, "TXD (b)", "1101 1110 01-- ----")
|
||||
INST(TXQ, "TXQ", "1101 1111 0100 1---")
|
||||
INST(TXQ_b, "TXQ (b)", "1101 1111 0101 0---")
|
||||
INST(VABSDIFF, "VABSDIFF", "0101 0100 ---- ----")
|
||||
|
@ -317,14 +317,6 @@ void TranslatorVisitor::TXA(u64) {
|
||||
ThrowNotImplemented(Opcode::TXA);
|
||||
}
|
||||
|
||||
void TranslatorVisitor::TXD(u64) {
|
||||
ThrowNotImplemented(Opcode::TXD);
|
||||
}
|
||||
|
||||
void TranslatorVisitor::TXD_b(u64) {
|
||||
ThrowNotImplemented(Opcode::TXD_b);
|
||||
}
|
||||
|
||||
void TranslatorVisitor::VABSDIFF(u64) {
|
||||
ThrowNotImplemented(Opcode::VABSDIFF);
|
||||
}
|
||||
|
@ -0,0 +1,180 @@
|
||||
// Copyright 2021 yuzu Emulator Project
|
||||
// Licensed under GPLv2 or any later version
|
||||
// Refer to the license.txt file included.
|
||||
|
||||
#include <optional>
|
||||
|
||||
#include "common/bit_field.h"
|
||||
#include "common/common_types.h"
|
||||
#include "shader_recompiler/frontend/ir/modifiers.h"
|
||||
#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
|
||||
|
||||
namespace Shader::Maxwell {
|
||||
namespace {
|
||||
|
||||
enum class TextureType : u64 {
|
||||
_1D,
|
||||
ARRAY_1D,
|
||||
_2D,
|
||||
ARRAY_2D,
|
||||
_3D,
|
||||
ARRAY_3D,
|
||||
CUBE,
|
||||
ARRAY_CUBE,
|
||||
};
|
||||
|
||||
Shader::TextureType GetType(TextureType type, bool dc) {
|
||||
switch (type) {
|
||||
case TextureType::_1D:
|
||||
return dc ? Shader::TextureType::Shadow1D : Shader::TextureType::Color1D;
|
||||
case TextureType::ARRAY_1D:
|
||||
return dc ? Shader::TextureType::ShadowArray1D : Shader::TextureType::ColorArray1D;
|
||||
case TextureType::_2D:
|
||||
return dc ? Shader::TextureType::Shadow2D : Shader::TextureType::Color2D;
|
||||
case TextureType::ARRAY_2D:
|
||||
return dc ? Shader::TextureType::ShadowArray2D : Shader::TextureType::ColorArray2D;
|
||||
case TextureType::_3D:
|
||||
return dc ? Shader::TextureType::Shadow3D : Shader::TextureType::Color3D;
|
||||
case TextureType::ARRAY_3D:
|
||||
throw NotImplementedException("3D array texture type");
|
||||
case TextureType::CUBE:
|
||||
return dc ? Shader::TextureType::ShadowCube : Shader::TextureType::ColorCube;
|
||||
case TextureType::ARRAY_CUBE:
|
||||
return dc ? Shader::TextureType::ShadowArrayCube : Shader::TextureType::ColorArrayCube;
|
||||
}
|
||||
throw NotImplementedException("Invalid texture type {}", type);
|
||||
}
|
||||
|
||||
IR::Value MakeOffset(TranslatorVisitor& v, IR::Reg reg, bool has_lod_clamp) {
|
||||
const IR::U32 value{v.X(reg)};
|
||||
const u32 base = has_lod_clamp ? 12 : 16;
|
||||
return v.ir.CompositeConstruct(
|
||||
v.ir.BitFieldExtract(value, v.ir.Imm32(base), v.ir.Imm32(4), true),
|
||||
v.ir.BitFieldExtract(value, v.ir.Imm32(base + 4), v.ir.Imm32(4), true));
|
||||
}
|
||||
|
||||
void Impl(TranslatorVisitor& v, u64 insn, bool is_bindless) {
|
||||
union {
|
||||
u64 raw;
|
||||
BitField<49, 1, u64> nodep;
|
||||
BitField<35, 1, u64> aoffi;
|
||||
BitField<50, 1, u64> lc;
|
||||
BitField<51, 3, IR::Pred> sparse_pred;
|
||||
BitField<0, 8, IR::Reg> dest_reg;
|
||||
BitField<8, 8, IR::Reg> coord_reg;
|
||||
BitField<20, 8, IR::Reg> derivate_reg;
|
||||
BitField<28, 3, TextureType> type;
|
||||
BitField<31, 4, u64> mask;
|
||||
BitField<36, 13, u64> cbuf_offset;
|
||||
} const txd{insn};
|
||||
|
||||
const bool has_lod_clamp = txd.lc != 0;
|
||||
if (has_lod_clamp) {
|
||||
throw NotImplementedException("TXD.LC - CLAMP is not implemented");
|
||||
}
|
||||
|
||||
IR::Value coords;
|
||||
u32 num_derivates;
|
||||
IR::Reg base_reg = txd.coord_reg;
|
||||
IR::Reg last_reg;
|
||||
IR::Value handle;
|
||||
if (!is_bindless) {
|
||||
handle = v.ir.Imm32(static_cast<u32>(txd.cbuf_offset.Value() * 4));
|
||||
} else {
|
||||
handle = v.X(base_reg++);
|
||||
}
|
||||
|
||||
const auto read_array{[&]() -> IR::F32 {
|
||||
return v.ir.ConvertUToF(32, 16,
|
||||
v.ir.BitFieldExtract(v.X(last_reg), v.ir.Imm32(0),
|
||||
v.ir.Imm32(has_lod_clamp ? 12 : 16)));
|
||||
}};
|
||||
switch (txd.type) {
|
||||
case TextureType::_1D: {
|
||||
coords = v.F(base_reg);
|
||||
num_derivates = 1;
|
||||
last_reg = base_reg + 1;
|
||||
break;
|
||||
}
|
||||
case TextureType::ARRAY_1D: {
|
||||
last_reg = base_reg + 1;
|
||||
coords = v.ir.CompositeConstruct(v.F(base_reg), read_array());
|
||||
num_derivates = 1;
|
||||
break;
|
||||
}
|
||||
case TextureType::_2D: {
|
||||
last_reg = base_reg + 2;
|
||||
coords = v.ir.CompositeConstruct(v.F(base_reg), v.F(base_reg + 1));
|
||||
num_derivates = 2;
|
||||
break;
|
||||
}
|
||||
case TextureType::ARRAY_2D: {
|
||||
last_reg = base_reg + 2;
|
||||
coords = v.ir.CompositeConstruct(v.F(base_reg), v.F(base_reg + 1), read_array());
|
||||
num_derivates = 2;
|
||||
break;
|
||||
}
|
||||
default:
|
||||
throw NotImplementedException("Invalid texture type");
|
||||
}
|
||||
|
||||
const IR::Reg derivate_reg{txd.derivate_reg};
|
||||
IR::Value derivates;
|
||||
switch (num_derivates) {
|
||||
case 1: {
|
||||
derivates = v.ir.CompositeConstruct(v.F(derivate_reg), v.F(derivate_reg + 1));
|
||||
break;
|
||||
}
|
||||
case 2: {
|
||||
derivates = v.ir.CompositeConstruct(v.F(derivate_reg), v.F(derivate_reg + 1),
|
||||
v.F(derivate_reg + 2), v.F(derivate_reg + 3));
|
||||
break;
|
||||
}
|
||||
default:
|
||||
throw NotImplementedException("Invalid texture type");
|
||||
}
|
||||
|
||||
IR::Value offset;
|
||||
if (txd.aoffi != 0) {
|
||||
offset = MakeOffset(v, last_reg, has_lod_clamp);
|
||||
}
|
||||
|
||||
IR::F32 lod_clamp;
|
||||
if (has_lod_clamp) {
|
||||
const IR::F32 conv4_8fixp_f = v.ir.Imm32(Common::BitCast<f32>(0x3b800000U));
|
||||
const IR::F32 tmp = v.ir.ConvertUToF(
|
||||
32, 16, v.ir.BitFieldExtract(v.X(last_reg), v.ir.Imm32(20), v.ir.Imm32(12)));
|
||||
lod_clamp = v.ir.FPMul(tmp, conv4_8fixp_f);
|
||||
}
|
||||
|
||||
IR::TextureInstInfo info{};
|
||||
info.type.Assign(GetType(txd.type, false));
|
||||
info.num_derivates.Assign(num_derivates);
|
||||
info.has_lod_clamp.Assign(has_lod_clamp ? 1 : 0);
|
||||
const IR::Value sample{[&]() -> IR::Value {
|
||||
return v.ir.ImageGradient(handle, coords, derivates, offset, lod_clamp, info);
|
||||
}()};
|
||||
|
||||
IR::Reg dest_reg{txd.dest_reg};
|
||||
for (size_t element = 0; element < 4; ++element) {
|
||||
if (((txd.mask >> element) & 1) == 0) {
|
||||
continue;
|
||||
}
|
||||
v.F(dest_reg, IR::F32{v.ir.CompositeExtract(sample, element)});
|
||||
++dest_reg;
|
||||
}
|
||||
if (txd.sparse_pred != IR::Pred::PT) {
|
||||
v.ir.SetPred(txd.sparse_pred, v.ir.LogicalNot(v.ir.GetSparseFromOp(sample)));
|
||||
}
|
||||
}
|
||||
} // Anonymous namespace
|
||||
|
||||
void TranslatorVisitor::TXD(u64 insn) {
|
||||
Impl(*this, insn, false);
|
||||
}
|
||||
|
||||
void TranslatorVisitor::TXD_b(u64 insn) {
|
||||
Impl(*this, insn, true);
|
||||
}
|
||||
|
||||
} // namespace Shader::Maxwell
|
Loading…
Reference in New Issue
Block a user