yuzu-emu/yuzu
1
0
Fork 0
mirror of https://github.com/yuzu-emu/yuzu.git synced 2024-11-27 03:14:17 +01:00
Code Issues Packages Projects Releases Wiki Activity

Added FMUL asserts

Browse Source
This commit is contained in:
David Marcec 2018-09-01 19:05:10 +10:00
parent c69dc5acf9
commit 6f8ed9508d
2 changed files with 15 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/video_core/engines/shader_bytecode.h
View File

@ -332,7 +332,12 @@ union Instruction {
} ipa; } ipa;
union { union {
BitField<39, 2, u64> tab5cb8_2;
BitField<41, 3, u64> tab5c68_1;
BitField<44, 2, u64> tab5c68_0;
BitField<47, 1, u64> cc;
BitField<48, 1, u64> negate_b; BitField<48, 1, u64> negate_b;
BitField<50, 1, u64> saturate;
} fmul; } fmul;
union { union {

10
src/video_core/renderer_opengl/gl_shader_decompiler.cpp
View File

@ -1038,6 +1038,16 @@ private:
case OpCode::Id::FMUL_R: case OpCode::Id::FMUL_R:
case OpCode::Id::FMUL_IMM: { case OpCode::Id::FMUL_IMM: {
// FMUL does not have 'abs' bits and only the second operand has a 'neg' bit. // FMUL does not have 'abs' bits and only the second operand has a 'neg' bit.
ASSERT_MSG(instr.fmul.tab5cb8_2 == 0, "FMUL tab5cb8_2({}) is not implemented",
instr.fmul.tab5cb8_2.Value());
ASSERT_MSG(instr.fmul.tab5c68_1 == 0, "FMUL tab5cb8_1({}) is not implemented",
instr.fmul.tab5c68_1.Value());
ASSERT_MSG(instr.fmul.tab5c68_0 == 1, "FMUL tab5cb8_0({}) is not implemented",
instr.fmul.tab5c68_0
.Value()); // SMO typical sends 1 here which seems to be the default
ASSERT_MSG(instr.fmul.cc == 0, "FMUL cc is not implemented");
ASSERT_MSG(instr.fmul.saturate == 0, "FMUL saturate is not implemented");
op_b = GetOperandAbsNeg(op_b, false, instr.fmul.negate_b); op_b = GetOperandAbsNeg(op_b, false, instr.fmul.negate_b);
regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " * " + op_b, 1, 1, regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " * " + op_b, 1, 1,
instr.alu.saturate_d); instr.alu.saturate_d);