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Merge pull request #369 from Subv/shader_instr2
ShaderGen: Implemented fsetp/kil and predicated instruction execution.
This commit is contained in:
bunnei
GitHub
commit
8ac3a3f45e
@ -13,6 +13,9 @@ namespace Tegra {
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namespace Shader {
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struct Register {
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// Register 255 is special cased to always be 0
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static constexpr size_t ZeroIndex = 255;
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constexpr Register() = default;
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constexpr Register(u64 value) : value(value) {}
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@ -106,6 +109,8 @@ union OpCode {
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FSETP_R = 0x5BB,
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FSETP_C = 0x4BB,
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FSETP_IMM = 0x36B,
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FSETP_NEG_IMM = 0x37B,
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EXIT = 0xE30,
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KIL = 0xE33,
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@ -121,6 +126,7 @@ union OpCode {
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Ffma,
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Flow,
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Memory,
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FloatPredicate,
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Unknown,
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};
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@ -161,6 +167,9 @@ union OpCode {
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case Id::FSETP_C:
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case Id::KIL:
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return op4;
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case Id::FSETP_IMM:
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case Id::FSETP_NEG_IMM:
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return Id::FSETP_IMM;
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}
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switch (op5) {
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@ -238,8 +247,9 @@ union OpCode {
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info_table[Id::FMUL_C] = {Type::Arithmetic, "fmul_c"};
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info_table[Id::FMUL_IMM] = {Type::Arithmetic, "fmul_imm"};
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info_table[Id::FMUL32_IMM] = {Type::Arithmetic, "fmul32_imm"};
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info_table[Id::FSETP_C] = {Type::Arithmetic, "fsetp_c"};
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info_table[Id::FSETP_R] = {Type::Arithmetic, "fsetp_r"};
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info_table[Id::FSETP_C] = {Type::FloatPredicate, "fsetp_c"};
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info_table[Id::FSETP_R] = {Type::FloatPredicate, "fsetp_r"};
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info_table[Id::FSETP_IMM] = {Type::FloatPredicate, "fsetp_imm"};
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info_table[Id::EXIT] = {Type::Trivial, "exit"};
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info_table[Id::IPA] = {Type::Trivial, "ipa"};
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info_table[Id::KIL] = {Type::Flow, "kil"};
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@ -283,7 +293,23 @@ namespace Shader {
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enum class Pred : u64 {
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UnusedIndex = 0x7,
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NeverExecute = 0xf,
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NeverExecute = 0xF,
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};
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enum class PredCondition : u64 {
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LessThan = 1,
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Equal = 2,
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LessEqual = 3,
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GreaterThan = 4,
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NotEqual = 5,
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GreaterEqual = 6,
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// TODO(Subv): Other condition types
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};
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enum class PredOperation : u64 {
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And = 0,
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Or = 1,
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Xor = 2,
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};
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enum class SubOp : u64 {
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@ -305,7 +331,11 @@ union Instruction {
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OpCode opcode;
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BitField<0, 8, Register> gpr0;
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BitField<8, 8, Register> gpr8;
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BitField<16, 4, Pred> pred;
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union {
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BitField<16, 4, Pred> full_pred;
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BitField<16, 3, u64> pred_index;
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} pred;
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BitField<19, 1, u64> negate_pred;
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BitField<20, 8, Register> gpr20;
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BitField<20, 7, SubOp> sub_op;
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BitField<28, 8, Register> gpr28;
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@ -343,6 +373,20 @@ union Instruction {
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BitField<49, 1, u64> negate_c;
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} ffma;
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union {
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BitField<0, 3, u64> pred0;
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BitField<3, 3, u64> pred3;
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BitField<7, 1, u64> abs_a;
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BitField<39, 3, u64> pred39;
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BitField<42, 1, u64> neg_pred;
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BitField<43, 1, u64> neg_a;
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BitField<44, 1, u64> abs_b;
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BitField<45, 2, PredOperation> op;
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BitField<47, 1, u64> ftz;
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BitField<48, 4, PredCondition> cond;
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BitField<56, 1, u64> neg_b;
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} fsetp;
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BitField<61, 1, u64> is_b_imm;
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BitField<60, 1, u64> is_b_gpr;
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BitField<59, 1, u64> is_c_gpr;
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@ -220,6 +220,8 @@ private:
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/// Generates code representing a temporary (GPR) register.
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std::string GetRegister(const Register& reg, unsigned elem = 0) {
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if (reg == Register::ZeroIndex)
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return "0";
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if (stage == Maxwell3D::Regs::ShaderStage::Fragment && reg < 4) {
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// GPRs 0-3 are output color for the fragment shader
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return std::string{"color."} + "rgba"[(reg + elem) & 3];
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@ -276,6 +278,52 @@ private:
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shader.AddLine(dest + " = " + src + ";");
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}
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/*
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* Writes code that assigns a predicate boolean variable.
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* @param pred The id of the predicate to write to.
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* @param value The expression value to assign to the predicate.
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*/
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void SetPredicate(u64 pred, const std::string& value) {
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using Tegra::Shader::Pred;
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// Can't assign to the constant predicate.
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ASSERT(pred != static_cast<u64>(Pred::UnusedIndex));
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std::string variable = 'p' + std::to_string(pred);
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shader.AddLine(variable + " = " + value + ';');
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declr_predicates.insert(std::move(variable));
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}
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/*
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* Returns the condition to use in the 'if' for a predicated instruction.
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* @param instr Instruction to generate the if condition for.
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* @returns string containing the predicate condition.
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*/
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std::string GetPredicateCondition(Instruction instr) const {
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using Tegra::Shader::Pred;
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ASSERT(instr.pred.pred_index != static_cast<u64>(Pred::UnusedIndex));
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std::string variable =
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'p' + std::to_string(static_cast<u64>(instr.pred.pred_index.Value()));
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if (instr.negate_pred) {
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return "!(" + variable + ')';
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}
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return variable;
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}
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/*
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* Returns whether the instruction at the specified offset is a 'sched' instruction.
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* Sched instructions always appear before a sequence of 3 instructions.
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*/
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bool IsSchedInstruction(u32 offset) const {
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// sched instructions appear once every 4 instructions.
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static constexpr size_t SchedPeriod = 4;
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u32 absolute_offset = offset - main_offset;
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return (absolute_offset % SchedPeriod) == 0;
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}
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/**
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* Compiles a single instruction from Tegra to GLSL.
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* @param offset the offset of the Tegra shader instruction.
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@ -283,10 +331,24 @@ private:
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* + 1. If the current instruction always terminates the program, returns PROGRAM_END.
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*/
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u32 CompileInstr(u32 offset) {
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// Ignore sched instructions when generating code.
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if (IsSchedInstruction(offset))
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return offset + 1;
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const Instruction instr = {program_code[offset]};
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shader.AddLine("// " + std::to_string(offset) + ": " + OpCode::GetInfo(instr.opcode).name);
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using Tegra::Shader::Pred;
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ASSERT_MSG(instr.pred.full_pred != Pred::NeverExecute,
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"NeverExecute predicate not implemented");
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if (instr.pred.pred_index != static_cast<u64>(Pred::UnusedIndex)) {
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shader.AddLine("if (" + GetPredicateCondition(instr) + ')');
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shader.AddLine('{');
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++shader.scope;
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}
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switch (OpCode::GetInfo(instr.opcode).type) {
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case OpCode::Type::Arithmetic: {
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std::string dest = GetRegister(instr.gpr0);
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@ -450,14 +512,70 @@ private:
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}
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break;
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}
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case OpCode::Type::FloatPredicate: {
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std::string op_a = instr.fsetp.neg_a ? "-" : "";
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op_a += GetRegister(instr.gpr8);
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if (instr.fsetp.abs_a) {
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op_a = "abs(" + op_a + ')';
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}
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std::string op_b{};
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if (instr.is_b_imm) {
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if (instr.fsetp.neg_b) {
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// Only the immediate version of fsetp has a neg_b bit.
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op_b += '-';
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}
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op_b += '(' + GetImmediate19(instr) + ')';
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} else {
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if (instr.is_b_gpr) {
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op_b += GetRegister(instr.gpr20);
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} else {
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op_b += GetUniform(instr.uniform);
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}
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}
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if (instr.fsetp.abs_b) {
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op_b = "abs(" + op_b + ')';
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}
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using Tegra::Shader::Pred;
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ASSERT_MSG(instr.fsetp.pred0 == static_cast<u64>(Pred::UnusedIndex) &&
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instr.fsetp.pred39 == static_cast<u64>(Pred::UnusedIndex),
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"Compound predicates are not implemented");
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// We can't use the constant predicate as destination.
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ASSERT(instr.fsetp.pred3 != static_cast<u64>(Pred::UnusedIndex));
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using Tegra::Shader::PredCondition;
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switch (instr.fsetp.cond) {
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case PredCondition::LessThan:
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SetPredicate(instr.fsetp.pred3, '(' + op_a + ") < (" + op_b + ')');
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break;
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case PredCondition::Equal:
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SetPredicate(instr.fsetp.pred3, '(' + op_a + ") == (" + op_b + ')');
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break;
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default:
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NGLOG_CRITICAL(HW_GPU, "Unhandled predicate condition: {} (a: {}, b: {})",
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static_cast<unsigned>(instr.fsetp.cond.Value()), op_a, op_b);
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UNREACHABLE();
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}
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break;
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}
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default: {
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switch (instr.opcode.EffectiveOpCode()) {
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case OpCode::Id::EXIT: {
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ASSERT_MSG(instr.pred.pred_index == static_cast<u64>(Pred::UnusedIndex),
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"Predicated exits not implemented");
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shader.AddLine("return true;");
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offset = PROGRAM_END - 1;
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break;
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}
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case OpCode::Id::KIL: {
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shader.AddLine("discard;");
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break;
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}
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case OpCode::Id::IPA: {
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const auto& attribute = instr.attribute.fmt28;
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std::string dest = GetRegister(instr.gpr0);
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@ -476,6 +594,12 @@ private:
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}
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}
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// Close the predicate condition scope.
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if (instr.pred.pred_index != static_cast<u64>(Pred::UnusedIndex)) {
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--shader.scope;
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shader.AddLine('}');
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}
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return offset + 1;
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}
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@ -605,6 +729,12 @@ private:
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declarations.AddNewLine();
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++const_buffer_layout;
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}
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declarations.AddNewLine();
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for (const auto& pred : declr_predicates) {
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declarations.AddLine("bool " + pred + " = false;");
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}
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declarations.AddNewLine();
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}
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private:
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@ -618,6 +748,7 @@ private:
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// Declarations
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std::set<std::string> declr_register;
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std::set<std::string> declr_predicates;
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std::set<Attribute::Index> declr_input_attribute;
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std::set<Attribute::Index> declr_output_attribute;
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std::array<ConstBufferEntry, Maxwell3D::Regs::MaxConstBuffers> declr_const_buffers;
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