mirror of
https://github.com/yuzu-emu/yuzu.git
synced 2024-11-23 12:55:41 +01:00
Merge pull request #644 from archshift/nihstro
Update nihstro submodule to the initial release version.
This commit is contained in:
bunnei
commit
8ecba90ff0
2
externals/nihstro
vendored
2
externals/nihstro
vendored
@ -1 +1 @@
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Subproject commit 0a8b4d221425f13e24a3cef9b02edc3221bab211
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Subproject commit 4a78588b308564f7ebae193e0ae00d9a0d5741d5
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@ -12,6 +12,7 @@
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#include "graphics_vertex_shader.h"
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using nihstro::OpCode;
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using nihstro::Instruction;
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using nihstro::SourceRegister;
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using nihstro::SwizzlePattern;
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@ -78,7 +79,7 @@ QVariant GraphicsVertexShaderModel::data(const QModelIndex& index, int role) con
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const SwizzlePattern& swizzle = info.swizzle_info[instr.common.operand_desc_id].pattern;
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// longest known instruction name: "setemit "
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output << std::setw(8) << std::left << instr.opcode.GetInfo().name;
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output << std::setw(8) << std::left << instr.opcode.Value().GetInfo().name;
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// e.g. "-c92.xyzw"
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static auto print_input = [](std::stringstream& output, const SourceRegister& input,
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@ -109,16 +110,16 @@ QVariant GraphicsVertexShaderModel::data(const QModelIndex& index, int role) con
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print_input_indexed(output, input, negate, swizzle_mask, address_register_name);
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};
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switch (instr.opcode.GetInfo().type) {
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case Instruction::OpCodeType::Trivial:
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switch (instr.opcode.Value().GetInfo().type) {
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case OpCode::Type::Trivial:
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// Nothing to do here
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break;
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case Instruction::OpCodeType::Arithmetic:
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case OpCode::Type::Arithmetic:
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{
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// Use custom code for special instructions
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switch (instr.opcode.EffectiveOpCode()) {
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case Instruction::OpCode::CMP:
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switch (instr.opcode.Value().EffectiveOpCode()) {
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case OpCode::Id::CMP:
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{
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// NOTE: CMP always writes both cc components, so we do not consider the dest mask here.
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output << std::setw(4) << std::right << "cc.";
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@ -142,13 +143,13 @@ QVariant GraphicsVertexShaderModel::data(const QModelIndex& index, int role) con
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default:
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{
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bool src_is_inverted = 0 != (instr.opcode.GetInfo().subtype & Instruction::OpCodeInfo::SrcInversed);
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bool src_is_inverted = 0 != (instr.opcode.Value().GetInfo().subtype & OpCode::Info::SrcInversed);
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if (instr.opcode.GetInfo().subtype & Instruction::OpCodeInfo::Dest) {
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if (instr.opcode.Value().GetInfo().subtype & OpCode::Info::Dest) {
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// e.g. "r12.xy__"
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output << std::setw(4) << std::right << instr.common.dest.GetName() + ".";
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output << std::setw(4) << std::right << instr.common.dest.Value().GetName() + ".";
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output << swizzle.DestMaskToString();
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} else if (instr.opcode.GetInfo().subtype == Instruction::OpCodeInfo::MOVA) {
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} else if (instr.opcode.Value().GetInfo().subtype == OpCode::Info::MOVA) {
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output << std::setw(4) << std::right << "a0.";
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output << swizzle.DestMaskToString();
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} else {
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@ -156,7 +157,7 @@ QVariant GraphicsVertexShaderModel::data(const QModelIndex& index, int role) con
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}
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output << " ";
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if (instr.opcode.GetInfo().subtype & Instruction::OpCodeInfo::Src1) {
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if (instr.opcode.Value().GetInfo().subtype & OpCode::Info::Src1) {
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SourceRegister src1 = instr.common.GetSrc1(src_is_inverted);
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print_input_indexed(output, src1, swizzle.negate_src1, swizzle.SelectorToString(false), instr.common.AddressRegisterName());
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} else {
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@ -164,7 +165,7 @@ QVariant GraphicsVertexShaderModel::data(const QModelIndex& index, int role) con
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}
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// TODO: In some cases, the Address Register is used as an index for SRC2 instead of SRC1
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if (instr.opcode.GetInfo().subtype & Instruction::OpCodeInfo::Src2) {
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if (instr.opcode.Value().GetInfo().subtype & OpCode::Info::Src2) {
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SourceRegister src2 = instr.common.GetSrc2(src_is_inverted);
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print_input(output, src2, swizzle.negate_src2, swizzle.SelectorToString(false));
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}
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@ -175,17 +176,17 @@ QVariant GraphicsVertexShaderModel::data(const QModelIndex& index, int role) con
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break;
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}
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case Instruction::OpCodeType::Conditional:
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case OpCode::Type::Conditional:
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{
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switch (instr.opcode.EffectiveOpCode()) {
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case Instruction::OpCode::LOOP:
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switch (instr.opcode.Value().EffectiveOpCode()) {
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case OpCode::Id::LOOP:
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output << "(unknown instruction format)";
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break;
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default:
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output << "if ";
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if (instr.opcode.GetInfo().subtype & Instruction::OpCodeInfo::HasCondition) {
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if (instr.opcode.Value().GetInfo().subtype & OpCode::Info::HasCondition) {
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const char* ops[] = {
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" || ", " && ", "", ""
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};
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@ -198,22 +199,22 @@ QVariant GraphicsVertexShaderModel::data(const QModelIndex& index, int role) con
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output << ((!instr.flow_control.refy) ? "!" : " ") << "cc.y";
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output << " ";
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} else if (instr.opcode.GetInfo().subtype & Instruction::OpCodeInfo::HasUniformIndex) {
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} else if (instr.opcode.Value().GetInfo().subtype & OpCode::Info::HasUniformIndex) {
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output << "b" << instr.flow_control.bool_uniform_id << " ";
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}
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u32 target_addr = instr.flow_control.dest_offset;
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u32 target_addr_else = instr.flow_control.dest_offset;
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if (instr.opcode.GetInfo().subtype & Instruction::OpCodeInfo::HasAlternative) {
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if (instr.opcode.Value().GetInfo().subtype & OpCode::Info::HasAlternative) {
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output << "else jump to 0x" << std::setw(4) << std::right << std::setfill('0') << 4 * instr.flow_control.dest_offset << " ";
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} else if (instr.opcode.GetInfo().subtype & Instruction::OpCodeInfo::HasExplicitDest) {
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} else if (instr.opcode.Value().GetInfo().subtype & OpCode::Info::HasExplicitDest) {
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output << "jump to 0x" << std::setw(4) << std::right << std::setfill('0') << 4 * instr.flow_control.dest_offset << " ";
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} else {
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// TODO: Handle other cases
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}
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if (instr.opcode.GetInfo().subtype & Instruction::OpCodeInfo::HasFinishPoint) {
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if (instr.opcode.Value().GetInfo().subtype & OpCode::Info::HasFinishPoint) {
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output << "(return on " << std::setw(4) << std::right << std::setfill('0')
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<< 4 * instr.flow_control.dest_offset + 4 * instr.flow_control.num_instructions << ")";
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}
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@ -17,6 +17,7 @@
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#include "vertex_shader.h"
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#include "debug_utils/debug_utils.h"
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using nihstro::OpCode;
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using nihstro::Instruction;
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using nihstro::RegisterType;
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using nihstro::SourceRegister;
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@ -154,10 +155,10 @@ static void ProcessShaderCode(VertexShaderState& state) {
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}
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};
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switch (instr.opcode.GetInfo().type) {
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case Instruction::OpCodeType::Arithmetic:
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switch (instr.opcode.Value().GetInfo().type) {
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case OpCode::Type::Arithmetic:
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{
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bool is_inverted = 0 != (instr.opcode.GetInfo().subtype & Instruction::OpCodeInfo::SrcInversed);
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bool is_inverted = 0 != (instr.opcode.Value().GetInfo().subtype & OpCode::Info::SrcInversed);
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// TODO: We don't really support this properly: For instance, the address register
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// offset needs to be applied to SRC2 instead, etc.
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// For now, we just abort in this situation.
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@ -197,15 +198,15 @@ static void ProcessShaderCode(VertexShaderState& state) {
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src2[3] = src2[3] * float24::FromFloat32(-1);
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}
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float24* dest = (instr.common.dest < 0x08) ? state.output_register_table[4*instr.common.dest.GetIndex()]
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: (instr.common.dest < 0x10) ? dummy_vec4_float24
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: (instr.common.dest < 0x20) ? &state.temporary_registers[instr.common.dest.GetIndex()][0]
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float24* dest = (instr.common.dest.Value() < 0x08) ? state.output_register_table[4*instr.common.dest.Value().GetIndex()]
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: (instr.common.dest.Value() < 0x10) ? dummy_vec4_float24
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: (instr.common.dest.Value() < 0x20) ? &state.temporary_registers[instr.common.dest.Value().GetIndex()][0]
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: dummy_vec4_float24;
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state.debug.max_opdesc_id = std::max<u32>(state.debug.max_opdesc_id, 1+instr.common.operand_desc_id);
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switch (instr.opcode.EffectiveOpCode()) {
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case Instruction::OpCode::ADD:
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switch (instr.opcode.Value().EffectiveOpCode()) {
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case OpCode::Id::ADD:
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{
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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@ -217,7 +218,7 @@ static void ProcessShaderCode(VertexShaderState& state) {
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break;
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}
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case Instruction::OpCode::MUL:
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case OpCode::Id::MUL:
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{
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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@ -229,7 +230,7 @@ static void ProcessShaderCode(VertexShaderState& state) {
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break;
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}
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case Instruction::OpCode::MAX:
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case OpCode::Id::MAX:
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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@ -238,11 +239,11 @@ static void ProcessShaderCode(VertexShaderState& state) {
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}
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break;
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case Instruction::OpCode::DP3:
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case Instruction::OpCode::DP4:
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case OpCode::Id::DP3:
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case OpCode::Id::DP4:
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{
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float24 dot = float24::FromFloat32(0.f);
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int num_components = (instr.opcode == Instruction::OpCode::DP3) ? 3 : 4;
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int num_components = (instr.opcode.Value() == OpCode::Id::DP3) ? 3 : 4;
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for (int i = 0; i < num_components; ++i)
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dot = dot + src1[i] * src2[i];
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@ -256,7 +257,7 @@ static void ProcessShaderCode(VertexShaderState& state) {
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}
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// Reciprocal
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case Instruction::OpCode::RCP:
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case OpCode::Id::RCP:
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{
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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@ -271,7 +272,7 @@ static void ProcessShaderCode(VertexShaderState& state) {
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}
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// Reciprocal Square Root
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case Instruction::OpCode::RSQ:
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case OpCode::Id::RSQ:
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{
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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@ -285,7 +286,7 @@ static void ProcessShaderCode(VertexShaderState& state) {
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break;
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}
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case Instruction::OpCode::MOVA:
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case OpCode::Id::MOVA:
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{
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for (int i = 0; i < 2; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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@ -298,7 +299,7 @@ static void ProcessShaderCode(VertexShaderState& state) {
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break;
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}
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case Instruction::OpCode::MOV:
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case OpCode::Id::MOV:
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{
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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@ -309,7 +310,7 @@ static void ProcessShaderCode(VertexShaderState& state) {
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break;
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}
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case Instruction::OpCode::CMP:
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case OpCode::Id::CMP:
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for (int i = 0; i < 2; ++i) {
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// TODO: Can you restrict to one compare via dest masking?
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@ -350,7 +351,7 @@ static void ProcessShaderCode(VertexShaderState& state) {
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default:
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LOG_ERROR(HW_GPU, "Unhandled arithmetic instruction: 0x%02x (%s): 0x%08x",
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(int)instr.opcode.Value(), instr.opcode.GetInfo().name, instr.hex);
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(int)instr.opcode.Value().EffectiveOpCode(), instr.opcode.Value().GetInfo().name, instr.hex);
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DEBUG_ASSERT(false);
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break;
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}
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@ -358,9 +359,9 @@ static void ProcessShaderCode(VertexShaderState& state) {
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break;
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}
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case Instruction::OpCodeType::MultiplyAdd:
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case OpCode::Type::MultiplyAdd:
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{
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if (instr.opcode.EffectiveOpCode() == Instruction::OpCode::MAD) {
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if (instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MAD) {
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const SwizzlePattern& swizzle = *(SwizzlePattern*)&swizzle_data[instr.mad.operand_desc_id];
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const float24* src1_ = LookupSourceRegister(instr.mad.src1);
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@ -408,9 +409,9 @@ static void ProcessShaderCode(VertexShaderState& state) {
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src3[3] = src3[3] * float24::FromFloat32(-1);
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}
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float24* dest = (instr.mad.dest < 0x08) ? state.output_register_table[4*instr.mad.dest.GetIndex()]
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: (instr.mad.dest < 0x10) ? dummy_vec4_float24
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: (instr.mad.dest < 0x20) ? &state.temporary_registers[instr.mad.dest.GetIndex()][0]
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float24* dest = (instr.mad.dest.Value() < 0x08) ? state.output_register_table[4*instr.mad.dest.Value().GetIndex()]
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: (instr.mad.dest.Value() < 0x10) ? dummy_vec4_float24
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: (instr.mad.dest.Value() < 0x20) ? &state.temporary_registers[instr.mad.dest.Value().GetIndex()][0]
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: dummy_vec4_float24;
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for (int i = 0; i < 4; ++i) {
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@ -421,7 +422,7 @@ static void ProcessShaderCode(VertexShaderState& state) {
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}
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} else {
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LOG_ERROR(HW_GPU, "Unhandled multiply-add instruction: 0x%02x (%s): 0x%08x",
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(int)instr.opcode.Value(), instr.opcode.GetInfo().name, instr.hex);
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(int)instr.opcode.Value().EffectiveOpCode(), instr.opcode.Value().GetInfo().name, instr.hex);
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}
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break;
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}
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@ -448,31 +449,31 @@ static void ProcessShaderCode(VertexShaderState& state) {
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};
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// Handle each instruction on its own
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switch (instr.opcode) {
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case Instruction::OpCode::END:
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switch (instr.opcode.Value()) {
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case OpCode::Id::END:
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exit_loop = true;
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break;
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case Instruction::OpCode::JMPC:
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case OpCode::Id::JMPC:
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if (evaluate_condition(state, instr.flow_control.refx, instr.flow_control.refy, instr.flow_control)) {
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state.program_counter = &shader_memory[instr.flow_control.dest_offset] - 1;
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}
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break;
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case Instruction::OpCode::JMPU:
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case OpCode::Id::JMPU:
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if (shader_uniforms.b[instr.flow_control.bool_uniform_id]) {
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state.program_counter = &shader_memory[instr.flow_control.dest_offset] - 1;
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}
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break;
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case Instruction::OpCode::CALL:
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case OpCode::Id::CALL:
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call(state,
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instr.flow_control.dest_offset,
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instr.flow_control.num_instructions,
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binary_offset + 1, 0, 0);
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break;
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case Instruction::OpCode::CALLU:
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case OpCode::Id::CALLU:
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if (shader_uniforms.b[instr.flow_control.bool_uniform_id]) {
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call(state,
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instr.flow_control.dest_offset,
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@ -481,7 +482,7 @@ static void ProcessShaderCode(VertexShaderState& state) {
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}
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break;
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case Instruction::OpCode::CALLC:
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case OpCode::Id::CALLC:
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if (evaluate_condition(state, instr.flow_control.refx, instr.flow_control.refy, instr.flow_control)) {
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call(state,
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instr.flow_control.dest_offset,
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@ -490,10 +491,10 @@ static void ProcessShaderCode(VertexShaderState& state) {
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}
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break;
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case Instruction::OpCode::NOP:
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case OpCode::Id::NOP:
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break;
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case Instruction::OpCode::IFU:
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case OpCode::Id::IFU:
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if (shader_uniforms.b[instr.flow_control.bool_uniform_id]) {
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call(state,
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binary_offset + 1,
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@ -508,7 +509,7 @@ static void ProcessShaderCode(VertexShaderState& state) {
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break;
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case Instruction::OpCode::IFC:
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case OpCode::Id::IFC:
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{
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// TODO: Do we need to consider swizzlers here?
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@ -527,7 +528,7 @@ static void ProcessShaderCode(VertexShaderState& state) {
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break;
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}
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case Instruction::OpCode::LOOP:
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case OpCode::Id::LOOP:
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{
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state.address_registers[2] = shader_uniforms.i[instr.flow_control.int_uniform_id].y;
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@ -542,7 +543,7 @@ static void ProcessShaderCode(VertexShaderState& state) {
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default:
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LOG_ERROR(HW_GPU, "Unhandled instruction: 0x%02x (%s): 0x%08x",
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(int)instr.opcode.Value(), instr.opcode.GetInfo().name, instr.hex);
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(int)instr.opcode.Value().EffectiveOpCode(), instr.opcode.Value().GetInfo().name, instr.hex);
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break;
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}
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