mirror of
https://github.com/yuzu-emu/yuzu.git
synced 2024-11-25 23:15:41 +01:00
Merge pull request #8188 from merryhime/jit-race-page-table-changed
dynarmic: Fix race when switching page tables
This commit is contained in:
bunnei
GitHub
commit
a29a8c6f78
@ -88,7 +88,7 @@ public:
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void CallSVC(u32 swi) override {
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parent.svc_swi = swi;
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parent.jit->HaltExecution(svc_call);
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parent.jit.load()->HaltExecution(svc_call);
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}
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void AddTicks(u64 ticks) override {
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@ -151,6 +151,13 @@ std::shared_ptr<Dynarmic::A32::Jit> ARM_Dynarmic_32::MakeJit(Common::PageTable*
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config.code_cache_size = 512_MiB;
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config.far_code_offset = 400_MiB;
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// null_jit
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if (!page_table) {
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// Don't waste too much memory on null_jit
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config.code_cache_size = 8_MiB;
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config.far_code_offset = 4_MiB;
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}
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// Safe optimizations
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if (Settings::values.cpu_debug_mode) {
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if (!Settings::values.cpuopt_page_tables) {
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@ -228,7 +235,7 @@ std::shared_ptr<Dynarmic::A32::Jit> ARM_Dynarmic_32::MakeJit(Common::PageTable*
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void ARM_Dynarmic_32::Run() {
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while (true) {
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const auto hr = jit->Run();
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const auto hr = jit.load()->Run();
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if (Has(hr, svc_call)) {
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Kernel::Svc::Call(system, svc_swi);
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}
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@ -239,7 +246,7 @@ void ARM_Dynarmic_32::Run() {
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}
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void ARM_Dynarmic_32::Step() {
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jit->Step();
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jit.load()->Step();
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}
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ARM_Dynarmic_32::ARM_Dynarmic_32(System& system_, CPUInterrupts& interrupt_handlers_,
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@ -249,24 +256,24 @@ ARM_Dynarmic_32::ARM_Dynarmic_32(System& system_, CPUInterrupts& interrupt_handl
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cb(std::make_unique<DynarmicCallbacks32>(*this)),
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cp15(std::make_shared<DynarmicCP15>(*this)), core_index{core_index_},
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exclusive_monitor{dynamic_cast<DynarmicExclusiveMonitor&>(exclusive_monitor_)},
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jit(MakeJit(nullptr)) {}
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null_jit{MakeJit(nullptr)}, jit{null_jit.get()} {}
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ARM_Dynarmic_32::~ARM_Dynarmic_32() = default;
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void ARM_Dynarmic_32::SetPC(u64 pc) {
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jit->Regs()[15] = static_cast<u32>(pc);
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jit.load()->Regs()[15] = static_cast<u32>(pc);
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}
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u64 ARM_Dynarmic_32::GetPC() const {
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return jit->Regs()[15];
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return jit.load()->Regs()[15];
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}
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u64 ARM_Dynarmic_32::GetReg(int index) const {
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return jit->Regs()[index];
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return jit.load()->Regs()[index];
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}
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void ARM_Dynarmic_32::SetReg(int index, u64 value) {
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jit->Regs()[index] = static_cast<u32>(value);
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jit.load()->Regs()[index] = static_cast<u32>(value);
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}
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u128 ARM_Dynarmic_32::GetVectorReg(int index) const {
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@ -276,11 +283,11 @@ u128 ARM_Dynarmic_32::GetVectorReg(int index) const {
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void ARM_Dynarmic_32::SetVectorReg(int index, u128 value) {}
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u32 ARM_Dynarmic_32::GetPSTATE() const {
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return jit->Cpsr();
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return jit.load()->Cpsr();
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}
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void ARM_Dynarmic_32::SetPSTATE(u32 cpsr) {
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jit->SetCpsr(cpsr);
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jit.load()->SetCpsr(cpsr);
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}
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u64 ARM_Dynarmic_32::GetTlsAddress() const {
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@ -301,7 +308,7 @@ void ARM_Dynarmic_32::SetTPIDR_EL0(u64 value) {
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void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) {
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Dynarmic::A32::Context context;
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jit->SaveContext(context);
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jit.load()->SaveContext(context);
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ctx.cpu_registers = context.Regs();
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ctx.extension_registers = context.ExtRegs();
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ctx.cpsr = context.Cpsr();
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@ -314,27 +321,27 @@ void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) {
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context.ExtRegs() = ctx.extension_registers;
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context.SetCpsr(ctx.cpsr);
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context.SetFpscr(ctx.fpscr);
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jit->LoadContext(context);
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jit.load()->LoadContext(context);
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}
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void ARM_Dynarmic_32::PrepareReschedule() {
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jit->HaltExecution(break_loop);
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jit.load()->HaltExecution(break_loop);
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}
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void ARM_Dynarmic_32::SignalInterrupt() {
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jit->HaltExecution(break_loop);
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jit.load()->HaltExecution(break_loop);
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}
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void ARM_Dynarmic_32::ClearInstructionCache() {
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jit->ClearCache();
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jit.load()->ClearCache();
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}
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void ARM_Dynarmic_32::InvalidateCacheRange(VAddr addr, std::size_t size) {
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jit->InvalidateCacheRange(static_cast<u32>(addr), size);
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jit.load()->InvalidateCacheRange(static_cast<u32>(addr), size);
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}
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void ARM_Dynarmic_32::ClearExclusiveState() {
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jit->ClearExclusiveState();
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jit.load()->ClearExclusiveState();
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}
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void ARM_Dynarmic_32::PageTableChanged(Common::PageTable& page_table,
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@ -345,13 +352,14 @@ void ARM_Dynarmic_32::PageTableChanged(Common::PageTable& page_table,
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auto key = std::make_pair(&page_table, new_address_space_size_in_bits);
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auto iter = jit_cache.find(key);
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if (iter != jit_cache.end()) {
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jit = iter->second;
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jit.store(iter->second.get());
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LoadContext(ctx);
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return;
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}
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jit = MakeJit(&page_table);
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std::shared_ptr new_jit = MakeJit(&page_table);
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jit.store(new_jit.get());
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LoadContext(ctx);
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jit_cache.emplace(key, jit);
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jit_cache.emplace(key, std::move(new_jit));
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}
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} // namespace Core
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@ -4,6 +4,7 @@
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#pragma once
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#include <atomic>
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#include <memory>
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#include <unordered_map>
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@ -80,7 +81,11 @@ private:
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std::shared_ptr<DynarmicCP15> cp15;
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std::size_t core_index;
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DynarmicExclusiveMonitor& exclusive_monitor;
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std::shared_ptr<Dynarmic::A32::Jit> jit;
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std::shared_ptr<Dynarmic::A32::Jit> null_jit;
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// A raw pointer here is fine; we never delete Jit instances.
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std::atomic<Dynarmic::A32::Jit*> jit;
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// SVC callback
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u32 svc_swi{};
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@ -109,7 +109,7 @@ public:
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break;
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}
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parent.jit->HaltExecution(Dynarmic::HaltReason::CacheInvalidation);
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parent.jit.load()->HaltExecution(Dynarmic::HaltReason::CacheInvalidation);
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}
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void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {
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@ -130,7 +130,7 @@ public:
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void CallSVC(u32 swi) override {
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parent.svc_swi = swi;
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parent.jit->HaltExecution(svc_call);
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parent.jit.load()->HaltExecution(svc_call);
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}
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void AddTicks(u64 ticks) override {
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@ -212,6 +212,13 @@ std::shared_ptr<Dynarmic::A64::Jit> ARM_Dynarmic_64::MakeJit(Common::PageTable*
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config.code_cache_size = 512_MiB;
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config.far_code_offset = 400_MiB;
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// null_jit
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if (!page_table) {
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// Don't waste too much memory on null_jit
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config.code_cache_size = 8_MiB;
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config.far_code_offset = 4_MiB;
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}
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// Safe optimizations
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if (Settings::values.cpu_debug_mode) {
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if (!Settings::values.cpuopt_page_tables) {
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@ -289,7 +296,7 @@ std::shared_ptr<Dynarmic::A64::Jit> ARM_Dynarmic_64::MakeJit(Common::PageTable*
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void ARM_Dynarmic_64::Run() {
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while (true) {
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const auto hr = jit->Run();
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const auto hr = jit.load()->Run();
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if (Has(hr, svc_call)) {
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Kernel::Svc::Call(system, svc_swi);
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}
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@ -300,7 +307,7 @@ void ARM_Dynarmic_64::Run() {
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}
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void ARM_Dynarmic_64::Step() {
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jit->Step();
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jit.load()->Step();
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}
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ARM_Dynarmic_64::ARM_Dynarmic_64(System& system_, CPUInterrupts& interrupt_handlers_,
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@ -309,40 +316,40 @@ ARM_Dynarmic_64::ARM_Dynarmic_64(System& system_, CPUInterrupts& interrupt_handl
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: ARM_Interface{system_, interrupt_handlers_, uses_wall_clock_},
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cb(std::make_unique<DynarmicCallbacks64>(*this)), core_index{core_index_},
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exclusive_monitor{dynamic_cast<DynarmicExclusiveMonitor&>(exclusive_monitor_)},
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jit(MakeJit(nullptr, 48)) {}
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null_jit{MakeJit(nullptr, 48)}, jit{null_jit.get()} {}
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ARM_Dynarmic_64::~ARM_Dynarmic_64() = default;
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void ARM_Dynarmic_64::SetPC(u64 pc) {
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jit->SetPC(pc);
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jit.load()->SetPC(pc);
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}
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u64 ARM_Dynarmic_64::GetPC() const {
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return jit->GetPC();
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return jit.load()->GetPC();
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}
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u64 ARM_Dynarmic_64::GetReg(int index) const {
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return jit->GetRegister(index);
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return jit.load()->GetRegister(index);
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}
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void ARM_Dynarmic_64::SetReg(int index, u64 value) {
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jit->SetRegister(index, value);
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jit.load()->SetRegister(index, value);
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}
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u128 ARM_Dynarmic_64::GetVectorReg(int index) const {
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return jit->GetVector(index);
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return jit.load()->GetVector(index);
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}
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void ARM_Dynarmic_64::SetVectorReg(int index, u128 value) {
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jit->SetVector(index, value);
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jit.load()->SetVector(index, value);
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}
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u32 ARM_Dynarmic_64::GetPSTATE() const {
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return jit->GetPstate();
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return jit.load()->GetPstate();
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}
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void ARM_Dynarmic_64::SetPSTATE(u32 pstate) {
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jit->SetPstate(pstate);
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jit.load()->SetPstate(pstate);
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}
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u64 ARM_Dynarmic_64::GetTlsAddress() const {
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@ -362,45 +369,47 @@ void ARM_Dynarmic_64::SetTPIDR_EL0(u64 value) {
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}
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void ARM_Dynarmic_64::SaveContext(ThreadContext64& ctx) {
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ctx.cpu_registers = jit->GetRegisters();
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ctx.sp = jit->GetSP();
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ctx.pc = jit->GetPC();
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ctx.pstate = jit->GetPstate();
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ctx.vector_registers = jit->GetVectors();
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ctx.fpcr = jit->GetFpcr();
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ctx.fpsr = jit->GetFpsr();
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Dynarmic::A64::Jit* j = jit.load();
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ctx.cpu_registers = j->GetRegisters();
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ctx.sp = j->GetSP();
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ctx.pc = j->GetPC();
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ctx.pstate = j->GetPstate();
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ctx.vector_registers = j->GetVectors();
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ctx.fpcr = j->GetFpcr();
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ctx.fpsr = j->GetFpsr();
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ctx.tpidr = cb->tpidr_el0;
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}
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void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) {
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jit->SetRegisters(ctx.cpu_registers);
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jit->SetSP(ctx.sp);
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jit->SetPC(ctx.pc);
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jit->SetPstate(ctx.pstate);
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jit->SetVectors(ctx.vector_registers);
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jit->SetFpcr(ctx.fpcr);
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jit->SetFpsr(ctx.fpsr);
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Dynarmic::A64::Jit* j = jit.load();
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j->SetRegisters(ctx.cpu_registers);
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j->SetSP(ctx.sp);
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j->SetPC(ctx.pc);
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j->SetPstate(ctx.pstate);
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j->SetVectors(ctx.vector_registers);
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j->SetFpcr(ctx.fpcr);
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j->SetFpsr(ctx.fpsr);
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SetTPIDR_EL0(ctx.tpidr);
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}
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void ARM_Dynarmic_64::PrepareReschedule() {
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jit->HaltExecution(break_loop);
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jit.load()->HaltExecution(break_loop);
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}
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void ARM_Dynarmic_64::SignalInterrupt() {
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jit->HaltExecution(break_loop);
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jit.load()->HaltExecution(break_loop);
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}
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void ARM_Dynarmic_64::ClearInstructionCache() {
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jit->ClearCache();
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jit.load()->ClearCache();
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}
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void ARM_Dynarmic_64::InvalidateCacheRange(VAddr addr, std::size_t size) {
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jit->InvalidateCacheRange(addr, size);
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jit.load()->InvalidateCacheRange(addr, size);
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}
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void ARM_Dynarmic_64::ClearExclusiveState() {
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jit->ClearExclusiveState();
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jit.load()->ClearExclusiveState();
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}
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void ARM_Dynarmic_64::PageTableChanged(Common::PageTable& page_table,
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@ -411,13 +420,14 @@ void ARM_Dynarmic_64::PageTableChanged(Common::PageTable& page_table,
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auto key = std::make_pair(&page_table, new_address_space_size_in_bits);
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auto iter = jit_cache.find(key);
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if (iter != jit_cache.end()) {
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jit = iter->second;
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jit.store(iter->second.get());
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LoadContext(ctx);
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return;
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}
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jit = MakeJit(&page_table, new_address_space_size_in_bits);
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std::shared_ptr new_jit = MakeJit(&page_table, new_address_space_size_in_bits);
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jit.store(new_jit.get());
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LoadContext(ctx);
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jit_cache.emplace(key, jit);
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jit_cache.emplace(key, std::move(new_jit));
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}
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} // namespace Core
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@ -4,6 +4,7 @@
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#pragma once
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#include <atomic>
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#include <memory>
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#include <unordered_map>
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@ -74,7 +75,10 @@ private:
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std::size_t core_index;
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DynarmicExclusiveMonitor& exclusive_monitor;
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std::shared_ptr<Dynarmic::A64::Jit> jit;
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std::shared_ptr<Dynarmic::A64::Jit> null_jit;
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// A raw pointer here is fine; we never delete Jit instances.
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std::atomic<Dynarmic::A64::Jit*> jit;
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// SVC callback
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u32 svc_swi{};
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