yuzu-emu/yuzu
1
0
Fork 0
mirror of https://github.com/yuzu-emu/yuzu.git synced 2024-11-30 19:44:16 +01:00
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #336 from lioncash/datqflag

Browse Source 
armemu: Correctly set the Q flag for a bunch of ops.
This commit is contained in:
bunnei 2014-12-23 10:41:01 -05:00
commit a7893adf20
3 changed files with 36 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
src/core/arm/interpreter/armemu.cpp
View File

@ -1670,7 +1670,7 @@ mainswitch:
op1 *= op2; op1 *= op2;
//printf("SMLA_INST:BB,op1=0x%x, op2=0x%x. Rn=0x%x\n", op1, op2, Rn); //printf("SMLA_INST:BB,op1=0x%x, op2=0x%x. Rn=0x%x\n", op1, op2, Rn);
if (AddOverflow(op1, Rn, op1 + Rn)) if (AddOverflow(op1, Rn, op1 + Rn))
SETS; SETQ;
state->Reg[BITS (16, 19)] = op1 + Rn; state->Reg[BITS (16, 19)] = op1 + Rn;
break; break;
} }
@ -1682,7 +1682,7 @@ mainswitch:
ARMword result = op1 + op2; ARMword result = op1 + op2;
if (AddOverflow(op1, op2, result)) { if (AddOverflow(op1, op2, result)) {
result = POS (result) ? 0x80000000 : 0x7fffffff; result = POS (result) ? 0x80000000 : 0x7fffffff;
SETS; SETQ;
} }
state->Reg[BITS (12, 15)] = result; state->Reg[BITS (12, 15)] = result;
break; break;
@ -1795,7 +1795,7 @@ mainswitch:
ARMword Rn = state->Reg[BITS(12, 15)]; ARMword Rn = state->Reg[BITS(12, 15)];
if (AddOverflow((ARMword)result, Rn, (ARMword)(result + Rn))) if (AddOverflow((ARMword)result, Rn, (ARMword)(result + Rn)))
SETS; SETQ;
result += Rn; result += Rn;
} }
state->Reg[BITS (16, 19)] = (ARMword)result; state->Reg[BITS (16, 19)] = (ARMword)result;
@ -1811,7 +1811,7 @@ mainswitch:
if (SubOverflow if (SubOverflow
(op1, op2, result)) { (op1, op2, result)) {
result = POS (result) ? 0x80000000 : 0x7fffffff; result = POS (result) ? 0x80000000 : 0x7fffffff;
SETS; SETQ;
} }
state->Reg[BITS (12, 15)] = result; state->Reg[BITS (12, 15)] = result;
@ -1934,13 +1934,13 @@ mainswitch:
if (AddOverflow if (AddOverflow
(op2, op2, op2d)) { (op2, op2, op2d)) {
SETS; SETQ;
op2d = POS (op2d) ? 0x80000000 : 0x7fffffff; op2d = POS (op2d) ? 0x80000000 : 0x7fffffff;
} }
result = op1 + op2d; result = op1 + op2d;
if (AddOverflow(op1, op2d, result)) { if (AddOverflow(op1, op2d, result)) {
SETS; SETQ;
result = POS (result) ? 0x80000000 : 0x7fffffff; result = POS (result) ? 0x80000000 : 0x7fffffff;
} }
@ -2053,13 +2053,13 @@ mainswitch:
ARMword result; ARMword result;
if (AddOverflow(op2, op2, op2d)) { if (AddOverflow(op2, op2, op2d)) {
SETS; SETQ;
op2d = POS (op2d) ? 0x80000000 : 0x7fffffff; op2d = POS (op2d) ? 0x80000000 : 0x7fffffff;
} }
result = op1 - op2d; result = op1 - op2d;
if (SubOverflow(op1, op2d, result)) { if (SubOverflow(op1, op2d, result)) {
SETS; SETQ;
result = POS (result) ? 0x80000000 : 0x7fffffff; result = POS (result) ? 0x80000000 : 0x7fffffff;
} }
@ -6478,22 +6478,28 @@ L_stm_s_takeabort:
const s16 rn_lo = (rn_val & 0xFFFF); const s16 rn_lo = (rn_val & 0xFFFF);
const s16 rn_hi = ((rn_val >> 16) & 0xFFFF); const s16 rn_hi = ((rn_val >> 16) & 0xFFFF);
// SMUAD const u32 product1 = (rn_lo * rm_lo);
if ((instr & 0xf0d0) == 0xf010) { const u32 product2 = (rn_hi * rm_hi);
state->Reg[rd_idx] = (rn_lo * rm_lo) + (rn_hi * rm_hi);
// SMUAD and SMLAD
if (BIT(6) == 0) {
state->Reg[rd_idx] = product1 + product2;
if (BITS(12, 15) != 15) {
state->Reg[rd_idx] += state->Reg[ra_idx];
ARMul_AddOverflowQ(state, product1 + product2, state->Reg[ra_idx]);
}
ARMul_AddOverflowQ(state, product1, product2);
} }
// SMUSD // SMUSD and SMLSD
else if ((instr & 0xf0d0) == 0xf050) {
state->Reg[rd_idx] = (rn_lo * rm_lo) - (rn_hi * rm_hi);
}
// SMLAD
else if ((instr & 0xd0) == 0x10) {
state->Reg[rd_idx] = (rn_lo * rm_lo) + (rn_hi * rm_hi) + (s32)state->Reg[ra_idx];
}
// SMLSD
else { else {
state->Reg[rd_idx] = ((rn_lo * rm_lo) - (rn_hi * rm_hi)) + (s32)state->Reg[ra_idx]; state->Reg[rd_idx] = product1 - product2;
if (BITS(12, 15) != 15)
state->Reg[rd_idx] += state->Reg[ra_idx];
} }
return 1; return 1;
} }
break; break;

8
src/core/arm/interpreter/armsupp.cpp
View File

@ -444,6 +444,14 @@ ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result)
ASSIGNV (AddOverflow (a, b, result)); ASSIGNV (AddOverflow (a, b, result));
} }
/* Assigns the Q flag if the given result is considered an overflow from the addition of a and b */
void ARMul_AddOverflowQ(ARMul_State* state, ARMword a, ARMword b)
{
u32 result = a + b;
if (((result ^ a) & (u32)0x80000000) && ((a ^ b) & (u32)0x80000000) == 0)
SETQ;
}
/* Assigns the C flag after an subtraction of a and b to give result. */ /* Assigns the C flag after an subtraction of a and b to give result. */
void void

1
src/core/arm/skyeye_common/armemu.h
View File

@ -602,6 +602,7 @@ extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword);
extern void ARMul_MSRCpsr (ARMul_State *, ARMword, ARMword); extern void ARMul_MSRCpsr (ARMul_State *, ARMword, ARMword);
extern void ARMul_SubOverflow (ARMul_State *, ARMword, ARMword, ARMword); extern void ARMul_SubOverflow (ARMul_State *, ARMword, ARMword, ARMword);
extern void ARMul_AddOverflow (ARMul_State *, ARMword, ARMword, ARMword); extern void ARMul_AddOverflow (ARMul_State *, ARMword, ARMword, ARMword);
extern void ARMul_AddOverflowQ(ARMul_State*, ARMword, ARMword);
extern void ARMul_SubCarry (ARMul_State *, ARMword, ARMword, ARMword); extern void ARMul_SubCarry (ARMul_State *, ARMword, ARMword, ARMword);
extern void ARMul_AddCarry (ARMul_State *, ARMword, ARMword, ARMword); extern void ARMul_AddCarry (ARMul_State *, ARMword, ARMword, ARMword);
extern tdstate ARMul_ThumbDecode (ARMul_State *, ARMword, ARMword, ARMword *); extern tdstate ARMul_ThumbDecode (ARMul_State *, ARMword, ARMword, ARMword *);