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buffer_cache: Mark uniform buffers as dirty if any enable bit changes
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a7e9756671
@ -142,7 +142,7 @@ public:
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void BindHostComputeBuffers();
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void SetEnabledUniformBuffers(size_t stage, u32 enabled);
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void SetEnabledUniformBuffers(const std::array<u32, NUM_STAGES>& mask);
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void SetEnabledComputeUniformBuffers(u32 enabled);
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@ -670,13 +670,13 @@ void BufferCache<P>::BindHostComputeBuffers() {
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}
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template <class P>
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void BufferCache<P>::SetEnabledUniformBuffers(size_t stage, u32 enabled) {
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void BufferCache<P>::SetEnabledUniformBuffers(const std::array<u32, NUM_STAGES>& mask) {
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if constexpr (HAS_PERSISTENT_UNIFORM_BUFFER_BINDINGS) {
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if (enabled_uniform_buffers[stage] != enabled) {
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dirty_uniform_buffers[stage] = ~u32{0};
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if (enabled_uniform_buffers != mask) {
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dirty_uniform_buffers.fill(~u32{0});
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}
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}
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enabled_uniform_buffers[stage] = enabled;
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enabled_uniform_buffers = mask;
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}
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template <class P>
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@ -100,6 +100,8 @@ GraphicsPipeline::GraphicsPipeline(const Device& device, TextureCache& texture_c
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base_uniform_bindings[stage + 1] += AccumulateCount(info.constant_buffer_descriptors);
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base_storage_bindings[stage + 1] += AccumulateCount(info.storage_buffers_descriptors);
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}
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enabled_uniform_buffers[stage] = info.constant_buffer_mask;
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const u32 num_tex_buffer_bindings{AccumulateCount(info.texture_buffer_descriptors)};
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num_texture_buffers[stage] += num_tex_buffer_bindings;
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num_textures += num_tex_buffer_bindings;
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@ -145,6 +147,7 @@ void GraphicsPipeline::Configure(bool is_indexed) {
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texture_cache.SynchronizeGraphicsDescriptors();
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buffer_cache.SetEnabledUniformBuffers(enabled_uniform_buffers);
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buffer_cache.runtime.SetBaseUniformBindings(base_uniform_bindings);
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buffer_cache.runtime.SetBaseStorageBindings(base_storage_bindings);
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buffer_cache.runtime.SetEnableStorageBuffers(use_storage_buffers);
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@ -153,7 +156,6 @@ void GraphicsPipeline::Configure(bool is_indexed) {
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const bool via_header_index{regs.sampler_index == Maxwell::SamplerIndex::ViaHeaderIndex};
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const auto config_stage{[&](size_t stage) {
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const Shader::Info& info{stage_infos[stage]};
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buffer_cache.SetEnabledUniformBuffers(stage, info.constant_buffer_mask);
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buffer_cache.UnbindGraphicsStorageBuffers(stage);
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if constexpr (Spec::has_storage_buffers) {
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size_t ssbo_index{};
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@ -99,6 +99,7 @@ private:
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u32 enabled_stages_mask{};
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std::array<Shader::Info, 5> stage_infos{};
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std::array<u32, 5> enabled_uniform_buffers{};
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std::array<u32, 5> base_uniform_bindings{};
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std::array<u32, 5> base_storage_bindings{};
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std::array<u32, 5> num_texture_buffers{};
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@ -218,6 +218,9 @@ GraphicsPipeline::GraphicsPipeline(Tegra::Engines::Maxwell3D& maxwell3d_,
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update_descriptor_queue{update_descriptor_queue_}, spv_modules{std::move(stages)} {
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std::ranges::transform(infos, stage_infos.begin(),
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[](const Shader::Info* info) { return info ? *info : Shader::Info{}; });
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std::ranges::transform(infos, enabled_uniform_buffers.begin(), [](const Shader::Info* info) {
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return info ? info->constant_buffer_mask : 0;
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});
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auto func{[this, &render_pass_cache, &descriptor_pool] {
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DescriptorLayoutBuilder builder{MakeBuilder(device, stage_infos)};
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@ -259,11 +262,12 @@ void GraphicsPipeline::ConfigureImpl(bool is_indexed) {
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texture_cache.SynchronizeGraphicsDescriptors();
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buffer_cache.SetEnabledUniformBuffers(enabled_uniform_buffers);
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const auto& regs{maxwell3d.regs};
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const bool via_header_index{regs.sampler_index == Maxwell::SamplerIndex::ViaHeaderIndex};
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const auto config_stage{[&](size_t stage) LAMBDA_FORCEINLINE {
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const Shader::Info& info{stage_infos[stage]};
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buffer_cache.SetEnabledUniformBuffers(stage, info.constant_buffer_mask);
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buffer_cache.UnbindGraphicsStorageBuffers(stage);
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if constexpr (Spec::has_storage_buffers) {
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size_t ssbo_index{};
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@ -128,7 +128,10 @@ private:
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std::vector<GraphicsPipeline*> transitions;
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std::array<vk::ShaderModule, NUM_STAGES> spv_modules;
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std::array<Shader::Info, NUM_STAGES> stage_infos;
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std::array<u32, 5> enabled_uniform_buffers{};
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vk::DescriptorSetLayout descriptor_set_layout;
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DescriptorAllocator descriptor_allocator;
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vk::PipelineLayout pipeline_layout;
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