yuzu-emu/yuzu
1
0
Fork 0
mirror of https://github.com/yuzu-emu/yuzu.git synced 2024-11-27 14:34:17 +01:00
Code Issues Packages Projects Releases Wiki Activity

shader_ir/conversion: Split int and float selector and implement F2F H1

Browse Source
This commit is contained in:
ReinUsesLisp 2019-08-28 16:09:33 -03:00
parent b13fbc25b8
commit e3534700d7
2 changed files with 24 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/video_core/engines/shader_bytecode.h
View File

@ -1006,7 +1006,6 @@ union Instruction {
} iset; } iset;
union { union {
BitField<41, 2, u64> selector;
BitField<45, 1, u64> negate_a; BitField<45, 1, u64> negate_a;
BitField<49, 1, u64> abs_a; BitField<49, 1, u64> abs_a;
BitField<10, 2, Register::Size> src_size; BitField<10, 2, Register::Size> src_size;
@ -1031,6 +1030,14 @@ union Instruction {
return static_cast<F2fRoundingOp>(rounding.Value() & rounding_mask); return static_cast<F2fRoundingOp>(rounding.Value() & rounding_mask);
} }
} f2f; } f2f;
union {
BitField<41, 2, u64> selector;
} int_src;
union {
BitField<41, 1, u64> selector;
} float_src;
} conversion; } conversion;
union { union {

34
src/video_core/shader/decode/conversion.cpp
View File

@ -14,6 +14,12 @@ using Tegra::Shader::Instruction;
using Tegra::Shader::OpCode; using Tegra::Shader::OpCode;
using Tegra::Shader::Register; using Tegra::Shader::Register;
namespace {
constexpr OperationCode GetFloatSelector(u64 selector) {
return selector == 0 ? OperationCode::FCastHalf0 : OperationCode::FCastHalf1;
}
} // Anonymous namespace
u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) { u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
const Instruction instr = {program_code[pc]}; const Instruction instr = {program_code[pc]};
const auto opcode = OpCode::Decode(instr); const auto opcode = OpCode::Decode(instr);
@ -22,7 +28,7 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
case OpCode::Id::I2I_R: case OpCode::Id::I2I_R:
case OpCode::Id::I2I_C: case OpCode::Id::I2I_C:
case OpCode::Id::I2I_IMM: { case OpCode::Id::I2I_IMM: {
UNIMPLEMENTED_IF(instr.conversion.selector.Value()); UNIMPLEMENTED_IF(instr.conversion.int_src.selector != 0);
UNIMPLEMENTED_IF(instr.conversion.dst_size != Register::Size::Word); UNIMPLEMENTED_IF(instr.conversion.dst_size != Register::Size::Word);
UNIMPLEMENTED_IF(instr.alu.saturate_d); UNIMPLEMENTED_IF(instr.alu.saturate_d);
@ -57,7 +63,7 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
case OpCode::Id::I2F_R: case OpCode::Id::I2F_R:
case OpCode::Id::I2F_C: case OpCode::Id::I2F_C:
case OpCode::Id::I2F_IMM: { case OpCode::Id::I2F_IMM: {
UNIMPLEMENTED_IF(instr.conversion.selector.Value()); UNIMPLEMENTED_IF(instr.conversion.int_src.selector != 0);
UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long); UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long);
UNIMPLEMENTED_IF_MSG(instr.generates_cc, UNIMPLEMENTED_IF_MSG(instr.generates_cc,
"Condition codes generation in I2F is not implemented"); "Condition codes generation in I2F is not implemented");
@ -93,7 +99,6 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
case OpCode::Id::F2F_R: case OpCode::Id::F2F_R:
case OpCode::Id::F2F_C: case OpCode::Id::F2F_C:
case OpCode::Id::F2F_IMM: { case OpCode::Id::F2F_IMM: {
UNIMPLEMENTED_IF(instr.conversion.selector.Value());
UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long); UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long);
UNIMPLEMENTED_IF(instr.conversion.src_size == Register::Size::Long); UNIMPLEMENTED_IF(instr.conversion.src_size == Register::Size::Long);
UNIMPLEMENTED_IF_MSG(instr.generates_cc, UNIMPLEMENTED_IF_MSG(instr.generates_cc,
@ -114,8 +119,10 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
}(); }();
if (instr.conversion.src_size == Register::Size::Short) { if (instr.conversion.src_size == Register::Size::Short) {
// TODO: figure where extract is sey in the encoding value = Operation(GetFloatSelector(instr.conversion.float_src.selector), NO_PRECISE,
value = Operation(OperationCode::FCastHalf0, PRECISE, value); std::move(value));
} else {
ASSERT(instr.conversion.float_src.selector == 0);
} }
value = GetOperandAbsNegFloat(value, instr.conversion.abs_a, instr.conversion.negate_a); value = GetOperandAbsNegFloat(value, instr.conversion.abs_a, instr.conversion.negate_a);
@ -170,19 +177,10 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
}(); }();
if (instr.conversion.src_size == Register::Size::Short) { if (instr.conversion.src_size == Register::Size::Short) {
const OperationCode cast = [instr] { value = Operation(GetFloatSelector(instr.conversion.float_src.selector), NO_PRECISE,
switch (instr.conversion.selector) { std::move(value));
case 0: } else {
return OperationCode::FCastHalf0; ASSERT(instr.conversion.float_src.selector == 0);
case 1:
return OperationCode::FCastHalf1;
default:
UNREACHABLE_MSG("Invalid selector={}",
static_cast<u32>(instr.conversion.selector));
return OperationCode::FCastHalf0;
}
}();
value = Operation(cast, NO_PRECISE, std::move(value));
} }
value = GetOperandAbsNegFloat(value, instr.conversion.abs_a, instr.conversion.negate_a); value = GetOperandAbsNegFloat(value, instr.conversion.abs_a, instr.conversion.negate_a);