Commit Graph

165 Commits

Author SHA1 Message Date
Frederic L
7a5eda5914 global: Use std::optional instead of boost::optional (#1578)
* get rid of boost::optional

* Remove optional references

* Use std::reference_wrapper for optional references

* Fix clang format

* Fix clang format part 2

* Adressed feedback

* Fix clang format and MacOS build
2018-10-30 00:03:25 -04:00
Subv
bb5eb4f20a GPU: Basic implementation of the Kepler Inline Memory engine (p2mf).
This engine writes data from a FIFO register into the configured address.
2018-09-12 13:57:08 -05:00
Markus Wick
c1b8cd9058 video_core: Refactor command_processor.
Inline the WriteReg helper as it is called ~20k times per frame.
2018-09-10 22:06:16 +02:00
Markus Wick
0cfb0bacb2 video_core: Move command buffer loop.
This moves the hot loop into video_core. This refactoring shall reduce the CPU overhead of calling ProcessCommandList.
2018-09-10 22:06:13 +02:00
Markus Wick
2081ed7db2 command_processor: Use std::array for bound_engines.
subchannel is a 3 bit field. So there must not be more than 8 bound engines.
And using a hashmap for up to 8 values is a bit overpowered.
2018-09-04 14:10:05 +02:00
Hexagon12
bc6d91a103 Lowered down the logging for methods 2018-08-07 19:51:40 +03:00
James Rowe
0d46f0df12 Update clang format 2018-07-02 21:45:47 -04:00
James Rowe
638956aa81 Rename logging macro back to LOG_* 2018-07-02 21:45:47 -04:00
Subv
987a170665 GPU: Partially implemented the Maxwell DMA engine.
Only tiled->linear and linear->tiled copies that aren't offsetted are supported for now. Queries are not supported. Swizzled copies are not supported.
2018-06-12 11:27:36 -05:00
Subv
e2db7a83f6 GPU: Allow command lists to rebind a channel to another engine in the middle of the command list. 2018-05-24 17:32:46 -05:00
Subv
a994446b6e GPU: Move the Maxwell3D macro uploading code to the inside of the Maxwell3D processor.
It doesn't belong in the PFIFO handler.
2018-04-25 11:55:27 -05:00
Subv
e2f2a49d2d GPU: Corrected the upper bound of the PFIFO method ids in the command processor. 2018-04-25 11:53:54 -05:00
Lioncash
b7551e457b
video-core: Move logging macros over to new fmt-capable ones 2018-04-25 09:13:57 -04:00
bunnei
239ac8abe2 memory_manager: Make GpuToCpuAddress return an optional. 2018-04-24 17:49:19 -04:00
bunnei
9e11a76e92 memory_manager: Use GPUVAdddr, not PAddr, for GPU addresses. 2018-04-24 17:40:43 -04:00
Subv
aa586fa268 GPU: Store uploaded GPU macros and keep track of the number of method parameters. 2018-03-18 11:51:46 -05:00
Subv
7ac8657432 GPU: Macros are specific to the Maxwell3D engine, so handle them internally. 2018-03-18 11:51:45 -05:00
Subv
29feece4b8 GPU: Process command mode 5 (IncreaseOnce) differently from other commands.
Accumulate all arguments before calling the desired method.

Note: Maybe we should do the same for the NonIncreasing mode?
2018-03-16 20:32:44 -05:00
Subv
6cddf9d88e Make a GPU class in VideoCore to contain the GPU state.
Also moved the GPU MemoryManager class to video_core since it makes more sense for it to be there.
2018-02-11 23:44:12 -05:00
Subv
e01a8f2187 GPU: Added a command processor to decode the GPU pushbuffers and forward the commands to their respective engines. 2018-02-11 22:42:48 -05:00
James Rowe
1d28b2e142 Remove references to PICA and rasterizers in video_core 2018-01-12 19:11:03 -07:00
bunnei
960a1416de hle: Initial implementation of NX service framework and IPC. 2017-10-14 22:18:42 -04:00
Huw Pascoe
b3b34a1e76 Extracted the attribute setup and draw commands into their own functions 2017-10-04 01:08:29 +01:00
James Rowe
19d41dcc6e Remove pipeline.gpu_mode and fix minor issues 2017-09-23 09:28:20 -06:00
James Rowe
ad0b57f407 GPU: Add draw for immediate and batch modes
PR #1461 introduced a regression where some games would change configuration
even while in the poorly named "drawing" mode, which broke the heuristic
citra was using to determine when to draw the batch. This change adds
back in a draw call for batching, and also adds in a draw call in
immediate mode each time it adds a triangle.
2017-09-11 09:21:43 -06:00
wwylele
0f35755572 pica/command_processor: build geometry pipeline and run geometry shader
The geometry pipeline manages data transfer between VS, GS and primitive assembler. It has known four modes:
 - no GS mode: sends VS output directly to the primitive assembler (what citra currently does)
 - GS mode 0: sends VS output to GS input registers, and sends GS output to primitive assembler
 - GS mode 1: sends VS output to GS uniform registers, and sends GS output to primitive assembler. It also takes an index from the index buffer at the beginning of each primitive for determine the primitive size.
 - GS mode 2: similar to mode 1, but doesn't take the index and uses a fixed primitive size.
hwtest shows that immediate mode also supports GS (at least for mode 0), so the geometry pipeline gets refactored into its own class for supporting both drawing mode.
In the immediate mode, some games don't set the pipeline registers to a valid value until the first attribute input, so a geometry pipeline reset flag is set in `pipeline.vs_default_attributes_setup.index` trigger, and the actual pipeline reconfigure is triggered in the first attribute input.
In the normal drawing mode with index buffer, the vertex cache is a little bit modified to support the geometry pipeline. Instead of OutputVertex, it now holds AttributeBuffer, which is the input to the geometry pipeline. The AttributeBuffer->OutputVertex conversion is done inside the pipeline vertex handler. The actual hardware vertex cache is believed to be implemented in a similar way (because this is the only way that makes sense).
Both geometry pipeline and GS unit rely on states preservation across drawing call, so they are put into the global state. In the future, the other three vertex shader units should be also placed in the global state, and a scheduler should be implemented on top of the four units. Note that the current gs_unit already allows running VS on it in the future.
2017-08-19 10:13:20 +03:00
wwylele
baa24f4ea9 pica: upload shared shader code to both unit 2017-08-07 10:30:05 +03:00
Yuri Kunde Schlesner
bae3799bd5 Merge pull request #2697 from wwylele/proctex
Implemented Procedural Texture (Texture Unit 3)
2017-05-24 21:37:42 -07:00
wwylele
ade45b5b99 pica/swrasterizer: implement procedural texture 2017-05-20 13:50:50 +03:00
wwylele
393fee10a2 pica: use correct register value for shader bool_uniforms
variable value is not masked. the masked and combined register value should be used instead
2017-05-17 22:14:09 +03:00
Jannik Vogel
ba722be2ac Pica: Write GS registers
This adds the handlers for the geometry shader register writes which will call the functions from the previous commit to update registers for the GS.
2017-05-12 16:22:37 +02:00
Jannik Vogel
3fd3775d35 Pica: Write shader registers in functions
The commit after this one adds GS register writes, so this moves the VS handlers into functions so they can be re-used and extended more easily.
2017-05-12 16:22:37 +02:00
Yuri Kunde Schlesner
60fc0b086f VideoCore: Split regs.h inclusions 2017-02-09 00:04:24 -08:00
Yuri Kunde Schlesner
602f57da38 VideoCore: Use union to index into Regs struct
Also remove some unused members.
2017-02-08 22:13:25 -08:00
Yuri Kunde Schlesner
5759d94b5c VideoCore: Move Regs to its own file 2017-02-04 13:59:12 -08:00
Yuri Kunde Schlesner
8fca90b5d5 VideoCore: Split geometry pipeline regs from Regs struct 2017-02-04 13:59:11 -08:00
Yuri Kunde Schlesner
9017093f58 VideoCore: Split texturing regs from Regs struct 2017-02-04 13:59:09 -08:00
Yuri Kunde Schlesner
000e78144c VideoCore: Split rasterizer regs from Regs struct 2017-02-04 13:08:47 -08:00
Yuri Kunde Schlesner
92bf5c88e6 VideoCore: Split shader output writing from semantic loading 2017-01-29 21:31:37 -08:00
Yuri Kunde Schlesner
335df895b9 VideoCore: Consistently use shader configuration to load attributes 2017-01-29 21:31:37 -08:00
Yuri Kunde Schlesner
fccb28d2e9 VideoCore: Use correct register for immediate mode attribute count 2017-01-29 21:31:36 -08:00
Yuri Kunde Schlesner
ab6954e942 VideoCore: Rename some types to more accurate names 2017-01-29 21:31:36 -08:00
Yuri Kunde Schlesner
bbc7844021 VideoCore: Change misleading register names
A few registers had names such as "count" or "number" when they actually
contained the maximum (that is, count - 1). This can easily lead to hard
to notice off by one errors.
2017-01-29 21:31:36 -08:00
Yuri Kunde Schlesner
0e9081b973 VideoCore/Shader: Move entry_point to SetupBatch 2017-01-25 18:53:25 -08:00
Yuri Kunde Schlesner
0f64274145 VideoCore/Shader: Move per-batch ShaderEngine state into ShaderSetup 2017-01-25 18:53:25 -08:00
Yuri Kunde Schlesner
6fa3687afc Shader: Remove OutputRegisters struct 2017-01-25 18:53:25 -08:00
Yuri Kunde Schlesner
dd4a1672a7 VideoCore/Shader: Split shader uniform state and shader engine
Currently there's only a single dummy implementation, which will be
split in a following commit.
2017-01-25 18:53:23 -08:00
Yuri Kunde Schlesner
1e1f939817 VideoCore/Shader: Use only entry_point as ShaderSetup param
This removes all implicit dependency of ShaderState on global PICA
state.
2017-01-25 18:53:23 -08:00
Yuri Kunde Schlesner
34d581f2dc VideoCore/Shader: Extract input vertex loading code into function 2017-01-25 18:53:20 -08:00
bunnei
29564d73bd Merge pull request #2319 from yuriks/profile-scopes
VideoCore: Make profiling scope more representative
2016-12-21 13:33:49 -05:00