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https://github.com/yuzu-emu/mbedtls.git
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vli_isZero and vli_clear assembly
Signed-off-by: Kevin Bracey <kevin.bracey@arm.com>
This commit is contained in:
Kevin Bracey
parent
4aea62569b
commit
3be252e252
162
tinycrypt/ecc.c
162
tinycrypt/ecc.c
@ -213,6 +213,63 @@ int uECC_curve_public_key_size(void)
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return 2 * NUM_ECC_BYTES;
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}
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#if defined MBEDTLS_HAVE_ASM && defined __CC_ARM
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__asm void uECC_vli_clear(uECC_word_t *vli)
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{
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#if NUM_ECC_WORDS != 8
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#error adjust ARM assembly to handle NUM_ECC_WORDS != 8
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#endif
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#if !defined __thumb__ || __TARGET_ARCH_THUMB < 4
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MOVS r1,#0
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MOVS r2,#0
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STMIA r0!,{r1,r2}
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STMIA r0!,{r1,r2}
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STMIA r0!,{r1,r2}
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STMIA r0!,{r1,r2}
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BX lr
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#else
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MOVS r1,#0
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STRD r1,r1,[r0,#0] // Only Thumb2 STRD can store same reg twice, not ARM
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STRD r1,r1,[r0,#8]
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STRD r1,r1,[r0,#16]
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STRD r1,r1,[r0,#24]
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BX lr
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#endif
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}
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#elif defined MBEDTLS_HAVE_ASM && defined __GNUC__ && defined __arm__
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void uECC_vli_clear(uECC_word_t *vli)
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{
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#if NUM_ECC_WORDS != 8
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#error adjust ARM assembly to handle NUM_ECC_WORDS != 8
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#endif
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#if !defined __thumb__ || !defined __thumb2__
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register uECC_word_t *r0 asm("r0") = vli;
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register uECC_word_t r1 asm("r1") = 0;
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register uECC_word_t r2 asm("r2") = 0;
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asm volatile (
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".syntax unified \n\t"
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"STMIA r0!,{r1,r2} \n\t"
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"STMIA r0!,{r1,r2} \n\t"
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"STMIA r0!,{r1,r2} \n\t"
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"STMIA r0!,{r1,r2} \n\t"
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: "+r" (r0)
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: "r" (r1), "r" (r2)
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: "memory"
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#else
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register uECC_word_t *r0 asm("r0") = vli;
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register uECC_word_t r1 asm("r1") = 0;
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asm volatile (
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"STRD r1,r1,[r0,#0] \n\t" // Only Thumb2 STRD can store same reg twice, not ARM
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"STRD r1,r1,[r0,#8] \n\t"
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"STRD r1,r1,[r0,#16] \n\t"
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"STRD r1,r1,[r0,#24] \n\t"
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:
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: "r" (r0), "r" (r1)
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: "memory"
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#endif
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);
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}
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#else
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void uECC_vli_clear(uECC_word_t *vli)
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{
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wordcount_t i;
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@ -220,7 +277,111 @@ void uECC_vli_clear(uECC_word_t *vli)
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vli[i] = 0;
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}
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}
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#endif
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#if defined MBEDTLS_HAVE_ASM && defined __CC_ARM
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__asm uECC_word_t uECC_vli_isZero(const uECC_word_t *vli)
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{
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#if NUM_ECC_WORDS != 8
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#error adjust ARM assembly to handle NUM_ECC_WORDS != 8
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#endif
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#if defined __thumb__ && __TARGET_ARCH_THUMB < 4
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LDMIA r0!,{r1,r2,r3}
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ORRS r1,r2
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ORRS r1,r3
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LDMIA r0!,{r2,r3}
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ORRS r1,r2
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ORRS r1,r3
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LDMIA r0,{r0,r2,r3}
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ORRS r1,r0
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ORRS r1,r2
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ORRS r1,r3
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RSBS r1,r1,#0 // C set if zero
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MOVS r0,#0
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ADCS r0,r0
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BX lr
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#else
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LDMIA r0!,{r1,r2,r3,ip}
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ORRS r1,r2
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ORRS r1,r3
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ORRS r1,ip
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LDMIA r0,{r0,r2,r3,ip}
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ORRS r1,r0
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ORRS r1,r2
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ORRS r1,r3
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ORRS r1,ip
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#ifdef __ARM_FEATURE_CLZ
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CLZ r0,r1 // 32 if zero
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LSRS r0,r0,#5
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#else
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RSBS r1,r1,#0 // C set if zero
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MOVS r0,#0
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ADCS r0,r0
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#endif
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BX lr
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#endif
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}
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#elif defined MBEDTLS_HAVE_ASM && defined __GNUC__ && defined __arm__
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uECC_word_t uECC_vli_isZero(const uECC_word_t *vli)
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{
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uECC_word_t ret;
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#if NUM_ECC_WORDS != 8
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#error adjust ARM assembly to handle NUM_ECC_WORDS != 8
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#endif
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#if defined __thumb__ && !defined __thumb2__
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register uECC_word_t r1 asm ("r1");
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register uECC_word_t r2 asm ("r2");
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register uECC_word_t r3 asm ("r3");
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asm volatile (
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".syntax unified \n\t"
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"LDMIA %[vli]!,{%[r1],%[r2],%[r3]} \n\t"
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"ORRS %[r1],%[r2] \n\t"
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"ORRS %[r1],%[r3] \n\t"
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"LDMIA %[vli]!,{%[r2],%[r3]} \n\t"
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"ORRS %[r1],%[r2] \n\t"
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"ORRS %[r1],%[r3] \n\t"
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"LDMIA %[vli],{%[vli],%[r2],%[r3]} \n\t"
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"ORRS %[r1],%[vli] \n\t"
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"ORRS %[r1],%[r2] \n\t"
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"ORRS %[r1],%[r3] \n\t"
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"RSBS %[r1],%[r1],#0 \n\t" // C set if zero
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"MOVS %[ret],#0 \n\t"
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"ADCS %[ret],r0 \n\t"
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: [ret]"=r" (ret), [r1]"=r" (r1), [r2]"=r" (r2), [r3]"=r" (r3)
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: [vli]"[ret]" (vli)
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: "cc", "memory"
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);
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#else
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register uECC_word_t r1 asm ("r1");
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register uECC_word_t r2 asm ("r2");
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register uECC_word_t r3 asm ("r3");
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register uECC_word_t ip asm ("ip");
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asm volatile (
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"LDMIA %[vli]!,{%[r1],%[r2],%[r3],%[ip]}\n\t"
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"ORRS %[r1],%[r2] \n\t"
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"ORRS %[r1],%[r3] \n\t"
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"ORRS %[r1],%[ip] \n\t"
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"LDMIA %[vli],{%[vli],%[r2],%[r3],%[ip]}\n\t"
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"ORRS %[r1],%[vli] \n\t"
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"ORRS %[r1],%[r2] \n\t"
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"ORRS %[r1],%[r3] \n\t"
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"ORRS %[r1],%[ip] \n\t"
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#if __ARM_ARCH >= 5
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"CLZ %[ret],%[r1] \n\t" // r0 = 32 if zero
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"LSRS %[ret],%[ret],#5 \n\t"
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#else
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"RSBS %[r1],%[r1],#0 \n\t" // C set if zero
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"MOVS %[ret],#0 \n\t"
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"ADCS %[ret],r0 \n\t"
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#endif
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: [ret]"=r" (ret), [r1]"=r" (r1), [r2]"=r" (r2), [r3]"=r" (r3), [ip]"=r" (ip)
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: [vli]"[ret]" (vli)
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: "cc", "memory"
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);
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#endif
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return ret;
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}
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#else
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uECC_word_t uECC_vli_isZero(const uECC_word_t *vli)
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{
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uECC_word_t bits = 0;
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@ -230,6 +391,7 @@ uECC_word_t uECC_vli_isZero(const uECC_word_t *vli)
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}
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return (bits == 0);
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}
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#endif
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uECC_word_t uECC_vli_testBit(const uECC_word_t *vli, bitcount_t bit)
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{
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