yuzu-emu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2024-10-20 23:38:17 +02:00
Code Issues Packages Projects Releases Wiki Activity

target/riscv: Extend the MIE CSR to support virtulisation

Browse Source 
Backports commit d0e53ce33ec8f66ffa597c634d50be73264aeadb from qemu
This commit is contained in:
Alistair Francis 2020-03-22 01:33:15 -04:00 committed by Lioncash
parent 6aabd67ef8
commit 1fd49ac6f0
1 changed files with 20 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
qemu/target/riscv/csr.c
View File

@ -244,8 +244,10 @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP)
#define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
static const target_ulong delegable_ints = S_MODE_INTERRUPTS; static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS; VS_MODE_INTERRUPTS;
static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
VS_MODE_INTERRUPTS;
static const target_ulong delegable_excps = static const target_ulong delegable_excps =
(1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) |
(1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) |
@ -633,13 +635,27 @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
static int read_sie(CPURISCVState *env, int csrno, target_ulong *val) static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
{ {
*val = env->mie & env->mideleg; if (riscv_cpu_virt_enabled(env)) {
/* Tell the guest the VS bits, shifted to the S bit locations */
*val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
} else {
*val = env->mie & env->mideleg;
}
return 0; return 0;
} }
static int write_sie(CPURISCVState *env, int csrno, target_ulong val) static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
{ {
target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg); target_ulong newval;
if (riscv_cpu_virt_enabled(env)) {
/* Shift the guests S bits to VS */
newval = (env->mie & ~VS_MODE_INTERRUPTS) |
((val << 1) & VS_MODE_INTERRUPTS);
} else {
newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
}
return write_mie(env, CSR_MIE, newval); return write_mie(env, CSR_MIE, newval);
} }