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target-arm: Eliminate unnecessary zero-extend in disas_bitfield

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For !SF, this initial ext32u can't be optimized away by the
current TCG code generator. (It would require backward bit
liveness propagation.)

Backports commit d3a77b42decd0cbfa62a5526e67d1d6d380c83a9 from qemu
This commit is contained in:
Richard Henderson 2018-02-11 01:35:31 -05:00 committed by Lioncash
parent c637a97270
commit 3173269986
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GPG Key ID: 4E3C3CC1031BA9C7
1 changed files with 6 additions and 1 deletions
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7
qemu/target-arm/translate-a64.c
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@ -3009,7 +3009,12 @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
}
tcg_rd = cpu_reg(s, rd);
tcg_tmp = read_cpu_reg(s, rn, sf);
/* Suppress the zero-extend for !sf. Since RI and SI are constrained
to be smaller than bitsize, we'll never reference data outside the
low 32-bits anyway. */
tcg_tmp = read_cpu_reg(s, rn, 1);
/* Recognize the common aliases. */
if (opc == 0) { /* SBFM */