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target/riscv: vector widening integer multiply instructions

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Backports 97b1cba39967251ab78b9d52fd9a4c62bb42d428
This commit is contained in:
LIU Zhiwei 2021-03-05 09:08:53 -05:00 committed by Lioncash
parent d144afdc45
commit 436e092e36
7 changed files with 138 additions and 0 deletions
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18
qemu/header_gen.py
View File

@ -6755,6 +6755,24 @@ riscv_symbols = (
'helper_vrem_vx_h',
'helper_vrem_vx_w',
'helper_vrem_vx_d',
'helpet_vwmul_vv_b',
'helpet_vwmul_vv_h',
'helpet_vwmul_vv_w',
'helpet_vwmulu_vv_b',
'helpet_vwmulu_vv_h',
'helpet_vwmulu_vv_w',
'helpet_vwmulsu_vv_b',
'helpet_vwmulsu_vv_h',
'helpet_vwmulsu_vv_w',
'helpet_vwmul_vx_b',
'helpet_vwmul_vx_h',
'helpet_vwmul_vx_w',
'helpet_vwmulu_vx_b',
'helpet_vwmulu_vx_h',
'helpet_vwmulu_vx_w',
'helpet_vwmulsu_vx_b',
'helpet_vwmulsu_vx_h',
'helpet_vwmulsu_vx_w',
'pmp_hart_has_privs',
'pmpaddr_csr_read',
'pmpaddr_csr_write',

18
qemu/riscv32.h
View File

@ -4191,6 +4191,24 @@
#define helper_vrem_vx_h helper_vrem_vx_h_riscv32
#define helper_vrem_vx_w helper_vrem_vx_w_riscv32
#define helper_vrem_vx_d helper_vrem_vx_d_riscv32
#define helpet_vwmul_vv_b helpet_vwmul_vv_b_riscv32
#define helpet_vwmul_vv_h helpet_vwmul_vv_h_riscv32
#define helpet_vwmul_vv_w helpet_vwmul_vv_w_riscv32
#define helpet_vwmulu_vv_b helpet_vwmulu_vv_b_riscv32
#define helpet_vwmulu_vv_h helpet_vwmulu_vv_h_riscv32
#define helpet_vwmulu_vv_w helpet_vwmulu_vv_w_riscv32
#define helpet_vwmulsu_vv_b helpet_vwmulsu_vv_b_riscv32
#define helpet_vwmulsu_vv_h helpet_vwmulsu_vv_h_riscv32
#define helpet_vwmulsu_vv_w helpet_vwmulsu_vv_w_riscv32
#define helpet_vwmul_vx_b helpet_vwmul_vx_b_riscv32
#define helpet_vwmul_vx_h helpet_vwmul_vx_h_riscv32
#define helpet_vwmul_vx_w helpet_vwmul_vx_w_riscv32
#define helpet_vwmulu_vx_b helpet_vwmulu_vx_b_riscv32
#define helpet_vwmulu_vx_h helpet_vwmulu_vx_h_riscv32
#define helpet_vwmulu_vx_w helpet_vwmulu_vx_w_riscv32
#define helpet_vwmulsu_vx_b helpet_vwmulsu_vx_b_riscv32
#define helpet_vwmulsu_vx_h helpet_vwmulsu_vx_h_riscv32
#define helpet_vwmulsu_vx_w helpet_vwmulsu_vx_w_riscv32
#define pmp_hart_has_privs pmp_hart_has_privs_riscv32
#define pmpaddr_csr_read pmpaddr_csr_read_riscv32
#define pmpaddr_csr_write pmpaddr_csr_write_riscv32

18
qemu/riscv64.h
View File

@ -4191,6 +4191,24 @@
#define helper_vrem_vx_h helper_vrem_vx_h_riscv64
#define helper_vrem_vx_w helper_vrem_vx_w_riscv64
#define helper_vrem_vx_d helper_vrem_vx_d_riscv64
#define helpet_vwmul_vv_b helpet_vwmul_vv_b_riscv64
#define helpet_vwmul_vv_h helpet_vwmul_vv_h_riscv64
#define helpet_vwmul_vv_w helpet_vwmul_vv_w_riscv64
#define helpet_vwmulu_vv_b helpet_vwmulu_vv_b_riscv64
#define helpet_vwmulu_vv_h helpet_vwmulu_vv_h_riscv64
#define helpet_vwmulu_vv_w helpet_vwmulu_vv_w_riscv64
#define helpet_vwmulsu_vv_b helpet_vwmulsu_vv_b_riscv64
#define helpet_vwmulsu_vv_h helpet_vwmulsu_vv_h_riscv64
#define helpet_vwmulsu_vv_w helpet_vwmulsu_vv_w_riscv64
#define helpet_vwmul_vx_b helpet_vwmul_vx_b_riscv64
#define helpet_vwmul_vx_h helpet_vwmul_vx_h_riscv64
#define helpet_vwmul_vx_w helpet_vwmul_vx_w_riscv64
#define helpet_vwmulu_vx_b helpet_vwmulu_vx_b_riscv64
#define helpet_vwmulu_vx_h helpet_vwmulu_vx_h_riscv64
#define helpet_vwmulu_vx_w helpet_vwmulu_vx_w_riscv64
#define helpet_vwmulsu_vx_b helpet_vwmulsu_vx_b_riscv64
#define helpet_vwmulsu_vx_h helpet_vwmulsu_vx_h_riscv64
#define helpet_vwmulsu_vx_w helpet_vwmulsu_vx_w_riscv64
#define pmp_hart_has_privs pmp_hart_has_privs_riscv64
#define pmpaddr_csr_read pmpaddr_csr_read_riscv64
#define pmpaddr_csr_write pmpaddr_csr_write_riscv64

19
qemu/target/riscv/helper.h
View File

@ -591,3 +591,22 @@ DEF_HELPER_6(vrem_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vrem_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vrem_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vrem_vx_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vwmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vwmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vwmulu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vwmulu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vwmulu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vwmulsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vwmulsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vwmulsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vwmul_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmul_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmul_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmulu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmulu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmulu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmulsu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmulsu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmulsu_vx_w, void, ptr, ptr, tl, ptr, env, i32)

6
qemu/target/riscv/insn32.decode
View File

@ -375,6 +375,12 @@ vremu_vv 100010 . ..... ..... 010 ..... 1010111 @r_vm
vremu_vx 100010 . ..... ..... 110 ..... 1010111 @r_vm
vrem_vv 100011 . ..... ..... 010 ..... 1010111 @r_vm
vrem_vx 100011 . ..... ..... 110 ..... 1010111 @r_vm
vwmulu_vv 111000 . ..... ..... 010 ..... 1010111 @r_vm
vwmulu_vx 111000 . ..... ..... 110 ..... 1010111 @r_vm
vwmulsu_vv 111010 . ..... ..... 010 ..... 1010111 @r_vm
vwmulsu_vx 111010 . ..... ..... 110 ..... 1010111 @r_vm
vwmul_vv 111011 . ..... ..... 010 ..... 1010111 @r_vm
vwmul_vx 111011 . ..... ..... 110 ..... 1010111 @r_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r

8
qemu/target/riscv/insn_trans/trans_rvv.inc.c
View File

@ -1522,3 +1522,11 @@ GEN_OPIVX_TRANS(vdivu_vx, opivx_check)
GEN_OPIVX_TRANS(vdiv_vx, opivx_check)
GEN_OPIVX_TRANS(vremu_vx, opivx_check)
GEN_OPIVX_TRANS(vrem_vx, opivx_check)
/* Vector Widening Integer Multiply Instructions */
GEN_OPIVV_WIDEN_TRANS(vwmul_vv, opivv_widen_check)
GEN_OPIVV_WIDEN_TRANS(vwmulu_vv, opivv_widen_check)
GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check)
GEN_OPIVX_WIDEN_TRANS(vwmul_vx)
GEN_OPIVX_WIDEN_TRANS(vwmulu_vx)
GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx)

51
qemu/target/riscv/vector_helper.c
View File

@ -864,6 +864,18 @@ GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w, clearl)
#define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t
#define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t
#define OP_SUS_D int64_t, uint64_t, int64_t, uint64_t, int64_t
#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t
#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t
#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t
#define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t
#define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t
#define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t
#define WOP_SUS_B int16_t, uint8_t, int8_t, uint16_t, int16_t
#define WOP_SUS_H int32_t, uint16_t, int16_t, uint32_t, int32_t
#define WOP_SUS_W int64_t, uint32_t, int32_t, uint64_t, int64_t
#define WOP_SSU_B int16_t, int8_t, uint8_t, int16_t, uint16_t
#define WOP_SSU_H int32_t, int16_t, uint16_t, int32_t, uint32_t
#define WOP_SSU_W int64_t, int32_t, uint32_t, int64_t, uint64_t
/* operation of two vector elements */
typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
@ -1827,3 +1839,42 @@ GEN_VEXT_VX(vrem_vx_b, 1, 1, clearb)
GEN_VEXT_VX(vrem_vx_h, 2, 2, clearh)
GEN_VEXT_VX(vrem_vx_w, 4, 4, clearl)
GEN_VEXT_VX(vrem_vx_d, 8, 8, clearq)
/* Vector Widening Integer Multiply Instructions */
RVVCALL(OPIVV2, vwmul_vv_b, WOP_SSS_B, H2, H1, H1, DO_MUL)
RVVCALL(OPIVV2, vwmul_vv_h, WOP_SSS_H, H4, H2, H2, DO_MUL)
RVVCALL(OPIVV2, vwmul_vv_w, WOP_SSS_W, H8, H4, H4, DO_MUL)
RVVCALL(OPIVV2, vwmulu_vv_b, WOP_UUU_B, H2, H1, H1, DO_MUL)
RVVCALL(OPIVV2, vwmulu_vv_h, WOP_UUU_H, H4, H2, H2, DO_MUL)
RVVCALL(OPIVV2, vwmulu_vv_w, WOP_UUU_W, H8, H4, H4, DO_MUL)
RVVCALL(OPIVV2, vwmulsu_vv_b, WOP_SUS_B, H2, H1, H1, DO_MUL)
RVVCALL(OPIVV2, vwmulsu_vv_h, WOP_SUS_H, H4, H2, H2, DO_MUL)
RVVCALL(OPIVV2, vwmulsu_vv_w, WOP_SUS_W, H8, H4, H4, DO_MUL)
GEN_VEXT_VV(vwmul_vv_b, 1, 2, clearh)
GEN_VEXT_VV(vwmul_vv_h, 2, 4, clearl)
GEN_VEXT_VV(vwmul_vv_w, 4, 8, clearq)
GEN_VEXT_VV(vwmulu_vv_b, 1, 2, clearh)
GEN_VEXT_VV(vwmulu_vv_h, 2, 4, clearl)
GEN_VEXT_VV(vwmulu_vv_w, 4, 8, clearq)
GEN_VEXT_VV(vwmulsu_vv_b, 1, 2, clearh)
GEN_VEXT_VV(vwmulsu_vv_h, 2, 4, clearl)
GEN_VEXT_VV(vwmulsu_vv_w, 4, 8, clearq)
RVVCALL(OPIVX2, vwmul_vx_b, WOP_SSS_B, H2, H1, DO_MUL)
RVVCALL(OPIVX2, vwmul_vx_h, WOP_SSS_H, H4, H2, DO_MUL)
RVVCALL(OPIVX2, vwmul_vx_w, WOP_SSS_W, H8, H4, DO_MUL)
RVVCALL(OPIVX2, vwmulu_vx_b, WOP_UUU_B, H2, H1, DO_MUL)
RVVCALL(OPIVX2, vwmulu_vx_h, WOP_UUU_H, H4, H2, DO_MUL)
RVVCALL(OPIVX2, vwmulu_vx_w, WOP_UUU_W, H8, H4, DO_MUL)
RVVCALL(OPIVX2, vwmulsu_vx_b, WOP_SUS_B, H2, H1, DO_MUL)
RVVCALL(OPIVX2, vwmulsu_vx_h, WOP_SUS_H, H4, H2, DO_MUL)
RVVCALL(OPIVX2, vwmulsu_vx_w, WOP_SUS_W, H8, H4, DO_MUL)
GEN_VEXT_VX(vwmul_vx_b, 1, 2, clearh)
GEN_VEXT_VX(vwmul_vx_h, 2, 4, clearl)
GEN_VEXT_VX(vwmul_vx_w, 4, 8, clearq)
GEN_VEXT_VX(vwmulu_vx_b, 1, 2, clearh)
GEN_VEXT_VX(vwmulu_vx_h, 2, 4, clearl)
GEN_VEXT_VX(vwmulu_vx_w, 4, 8, clearq)
GEN_VEXT_VX(vwmulsu_vx_b, 1, 2, clearh)
GEN_VEXT_VX(vwmulsu_vx_h, 2, 4, clearl)
GEN_VEXT_VX(vwmulsu_vx_w, 4, 8, clearq)