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arm/translate-a64: add FP16 FRECPE

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Now we have added f16 during the re-factoring we can simply call the
helper.

Backports commit fbd06e1e4b6566b4d727f9e553c819d034942f68 from qemu
This commit is contained in:
Alex Bennée 2018-03-08 19:12:02 -05:00 committed by Lioncash
parent 5f3864c2c2
commit 4ea310c131
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GPG Key ID: 4E3C3CC1031BA9C7
1 changed files with 8 additions and 0 deletions
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8
qemu/target/arm/translate-a64.c
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@ -11467,6 +11467,8 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x6d: /* FCMLE (zero) */
handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
return;
case 0x3d: /* FRECPE */
break;
case 0x18: /* FRINTN */
need_rmode = true;
only_in_vector = true;
@ -11586,6 +11588,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x3b: /* FCVTZS */
gen_helper_advsimd_f16tosinth(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus);
break;
case 0x3d: /* FRECPE */
gen_helper_recpe_f16(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus);
break;
case 0x5a: /* FCVTNU */
case 0x5b: /* FCVTMU */
case 0x5c: /* FCVTAU */
@ -11621,6 +11626,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x3b: /* FCVTZS */
gen_helper_advsimd_f16tosinth(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus);
break;
case 0x3d: /* FRECPE */
gen_helper_recpe_f16(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus);
break;
case 0x5a: /* FCVTNU */
case 0x5b: /* FCVTMU */
case 0x5c: /* FCVTAU */