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arm/translate-a64: add FP16 FRECPE
Now we have added f16 during the re-factoring we can simply call the helper. Backports commit fbd06e1e4b6566b4d727f9e553c819d034942f68 from qemu
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@ -11467,6 +11467,8 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
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case 0x6d: /* FCMLE (zero) */
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case 0x6d: /* FCMLE (zero) */
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handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
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handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
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return;
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return;
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case 0x3d: /* FRECPE */
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break;
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case 0x18: /* FRINTN */
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case 0x18: /* FRINTN */
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need_rmode = true;
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need_rmode = true;
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only_in_vector = true;
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only_in_vector = true;
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@ -11586,6 +11588,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
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case 0x3b: /* FCVTZS */
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case 0x3b: /* FCVTZS */
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gen_helper_advsimd_f16tosinth(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus);
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gen_helper_advsimd_f16tosinth(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus);
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break;
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break;
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case 0x3d: /* FRECPE */
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gen_helper_recpe_f16(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus);
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break;
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case 0x5a: /* FCVTNU */
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case 0x5a: /* FCVTNU */
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case 0x5b: /* FCVTMU */
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case 0x5b: /* FCVTMU */
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case 0x5c: /* FCVTAU */
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case 0x5c: /* FCVTAU */
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@ -11621,6 +11626,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
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case 0x3b: /* FCVTZS */
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case 0x3b: /* FCVTZS */
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gen_helper_advsimd_f16tosinth(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus);
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gen_helper_advsimd_f16tosinth(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus);
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break;
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break;
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case 0x3d: /* FRECPE */
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gen_helper_recpe_f16(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus);
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break;
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case 0x5a: /* FCVTNU */
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case 0x5a: /* FCVTNU */
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case 0x5b: /* FCVTMU */
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case 0x5b: /* FCVTMU */
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case 0x5c: /* FCVTAU */
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case 0x5c: /* FCVTAU */
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