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target/arm: Use store_reg_from_load in thumb2 code

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This function already includes the test for an interworking write
to PC from a load. Change the T32 LDM implementation to match the
A32 LDM implementation.

For LDM, the reordering of the tests does not change valid
behaviour because the only case that differs is has rn == 15,
which is UNPREDICTABLE.

Backports commit 69be3e13764111737e1a7a13bb0c231e4d5be756 from qemu
This commit is contained in:
Richard Henderson 2019-11-19 12:28:49 -05:00 committed by Lioncash
parent a2585ba590
commit 6ec6c71d50
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GPG Key ID: 4E3C3CC1031BA9C7
1 changed files with 3 additions and 9 deletions
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12
qemu/target/arm/translate.c
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@ -9907,13 +9907,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
/* Load. */
tmp = tcg_temp_new_i32(tcg_ctx);
gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
if (i == 15) {
gen_bx_excret(s, tmp);
} else if (i == rn) {
if (i == rn) {
loaded_var = tmp;
loaded_base = 1;
} else {
store_reg(s, i, tmp);
store_reg_from_load(s, i, tmp);
}
} else {
/* Store. */
@ -11054,11 +11052,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
tcg_temp_free_i32(tcg_ctx, addr);
goto illegal_op;
}
if (rs == 15) {
gen_bx_excret(s, tmp);
} else {
store_reg(s, rs, tmp);
}
store_reg_from_load(s, rs, tmp);
} else {
/* Store. */
tmp = load_reg(s, rs);