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target/riscv: Improve the scause logic

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No functional change, just making the code easier to read.

Backports commit 16fdb8ff64374ed51b246437e13043039a8eb9f9 from qemu
This commit is contained in:
Alistair Francis 2019-05-28 19:14:29 -04:00 committed by Lioncash
parent 4b0355dcfc
commit b44de569f0
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GPG Key ID: 4E3C3CC1031BA9C7
1 changed files with 1 additions and 1 deletions
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2
qemu/target/riscv/cpu_helper.c
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@ -500,7 +500,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
s = set_field(s, MSTATUS_SPP, env->priv);
s = set_field(s, MSTATUS_SIE, 0);
env->mstatus = s;
env->scause = cause | ~(((target_ulong)-1) >> async);
env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
env->sepc = env->pc;
env->sbadaddr = tval;
env->pc = (env->stvec >> 2 << 2) +