target/riscv: Add a riscv_cpu_is_32bit() helper function

Backports 51ae0cabc67c418264d5ae28214603aabc88b9b6

qemu/header_gen.py

@@ -7324,6 +7324,7 @@ riscv_symbols = (
     'riscv_cpu_fp_enabled',
     'riscv_cpu_get_fflags',
     'riscv_cpu_get_phys_page_debug',
+    'riscv_cpu_is_32bit',
     'riscv_cpu_list',
     'riscv_cpu_mmu_index',
     'riscv_cpu_register_types',

qemu/riscv32.h

@@ -4760,6 +4760,7 @@
 #define riscv_cpu_fp_enabled riscv_cpu_fp_enabled_riscv32
 #define riscv_cpu_get_fflags riscv_cpu_get_fflags_riscv32
 #define riscv_cpu_get_phys_page_debug riscv_cpu_get_phys_page_debug_riscv32
+#define riscv_cpu_is_32bit riscv_cpu_is_32bit_riscv32
 #define riscv_cpu_list riscv_cpu_list_riscv32
 #define riscv_cpu_mmu_index riscv_cpu_mmu_index_riscv32
 #define riscv_cpu_register_types riscv_cpu_register_types_riscv32

qemu/riscv64.h

@@ -4760,6 +4760,7 @@
 #define riscv_cpu_fp_enabled riscv_cpu_fp_enabled_riscv64
 #define riscv_cpu_get_fflags riscv_cpu_get_fflags_riscv64
 #define riscv_cpu_get_phys_page_debug riscv_cpu_get_phys_page_debug_riscv64
+#define riscv_cpu_is_32bit riscv_cpu_is_32bit_riscv64
 #define riscv_cpu_list riscv_cpu_list_riscv64
 #define riscv_cpu_mmu_index riscv_cpu_mmu_index_riscv64
 #define riscv_cpu_register_types riscv_cpu_register_types_riscv64

qemu/target/riscv/cpu.c

@@ -88,6 +88,15 @@ const char * const riscv_intr_names[] = {
     "reserved"
 };
 
+bool riscv_cpu_is_32bit(CPURISCVState *env)
+{
+    if (env->misa & RV64) {
+        return false;
+    }
+
+    return true;
+}
+
 static void set_misa(CPURISCVState *env, target_ulong misa)
 {
     env->misa_mask = env->misa = misa;

qemu/target/riscv/cpu.h

@@ -386,6 +386,8 @@ FIELD(TB_FLAGS, VILL, 8, 1)
 /* Is a Hypervisor instruction load/store allowed? */
 FIELD(TB_FLAGS, HLSX, 9, 1)
 
+bool riscv_cpu_is_32bit(CPURISCVState *env);
+
 /*
  * A simplification for VLMAX
  * = (1 << LMUL) * VLEN / (8 * (1 << SEW))