Commit Graph

5641 Commits

Author SHA1 Message Date
Bastian Koppelmann
1024ceb4df
target/riscv: Convert RV64I load/store insns to decodetree
this splits the 64-bit only instructions into its own decode file such
that we generate the decoder for these instructions only for the RISC-V
64 bit target.

Backports commit 7e45a682edc32ba90d6955215f062210531b835b from qemu
2019-03-18 16:02:16 -04:00
Bastian Koppelmann
65a415372b
target/riscv: Convert RV32I load/store insns to decodetree
Backports commit c1000d4e1bdb13857b601c425aca2fda9131283b from qemu
2019-03-18 15:59:43 -04:00
Bastian Koppelmann
55dc0038e8
target/riscv: Convert RVXI branch insns to decodetree
Backports commit 3cca75a6fe8b3f85e19559ffa64cb0be370d2814 from qemu
2019-03-18 15:58:16 -04:00
Bastian Koppelmann
5e5b3e9ea9
target/riscv: Activate decodetree and implemnt LUI & AUIPC
for now only LUI & AUIPC are decoded and translated. If decodetree fails, we
fall back to the old decoder.

Backports commit 2a53cff418335ccb4719e9a94fde55f6ebcc895d from qemu
2019-03-18 15:54:17 -04:00
Richard Henderson
4111a3a892
decodetree: Properly diagnose fields overflowing an insn
Previously this would result in an exception for shifting
the field mask by a negative number.

Backports commit 2decfc95583dc28add69810eaca6ada7b4b44d3a from qemu
2019-03-13 11:21:04 -04:00
Richard Henderson
fcb49bb6f6
decodetree: Prefix extract function names with decode_function
This makes it easier to name Formats within multiple decode files.

Backports commit 71ecf79bf40db20237a3cfc01cc407cc4cad8817 from qemu
2019-03-13 11:20:26 -04:00
Richard Henderson
1f57e9bedc
decodetree: Allow +- to begin a number initializing a field
Backports commit 263ac638a76a72841e3f513b14c515680703e084 from qemu
2019-03-13 11:19:56 -04:00
Richard Henderson
e18e116ce5
decodetree: Produce clean output for an empty input file
This is interesting for bisection, where an output file is plumbed,
but does not yet have patterns.

Backports commit 82bfac1c06cadeb5c7252734dc695d951185916c from qemu
2019-03-13 11:19:22 -04:00
Richard Henderson
190ee1657b
decodetree: Add --static-decode option
Like --decode, but do not drop 'static' qualifier.

Backports commit cd3e7fc18db43b296f413814cd4b72bcd6878bc4 from qemu
2019-03-13 11:18:43 -04:00
Richard Henderson
c8514cc538
decodetree: Allow grouping of overlapping patterns
Backports commit 0eff2df4a2ce677230119440f7eb057acffad5eb from qemu
2019-03-13 11:17:48 -04:00
Richard Henderson
0c1b2a5d5a
decodetree: Do not unconditionaly return from Pattern.output_code
As a consequence, the 'return false' gets pushed up one level.

This will allow us to perform some other action when the
translator returns failure.

Backports commit eb6b87fac70dd62e3f1286703db20c012e7a9611 from qemu
2019-03-13 11:13:48 -04:00
Philippe Mathieu-Daudé
edb21478b7
decodetree: Ensure build_tree does not include values outside insnmask
Reproduced with "scripts/decodetree.py /dev/null".

Backports commit 9b3186e38f00ae0cba36c096e3654f916699f336 from qemu
2019-03-13 11:12:24 -04:00
Wei Yang
20994eca53
exec.c: refactor function flatview_add_to_dispatch()
flatview_add_to_dispatch() registers page based on the condition of
*section*, which may looks like this:

|s|PPPPPPP|s|

where s stands for subpage and P for page.

The procedure of this function could be described as:

- register first subpage
- register page
- register last subpage

This means the procedure could be simplified into these three steps
instead of a loop iteration.

This patch refactors the function into three corresponding steps and
adds some comment to clarify it.

Backports commit 494d199727ba248c96326b4e1c97f86eb11a5ec7 from qemu
2019-03-11 17:00:46 -04:00
Philippe Mathieu-Daudé
963beb216d
configure: Disable W^X on OpenBSD
Since OpenBSD 6.0 [1], W^X is enforced by default [2].
TCG requires WX access. Disable W^X if it is available.
This fixes:

\# lm32-softmmu/qemu-system-lm32
Could not allocate dynamic translator buffer

\# sysctl kern.wxabort=1
kern.wxabort: 0 -> 1
\# lm32-softmmu/qemu-system-lm32
mmap: Not supported
Abort trap (core dumped)
\# gdb -q lm32-softmmu/qemu-system-lm32 qemu-system-lm32.core
(gdb) bt
\#0 0x000017e3c156c50a in _thread_sys___syscall () at {standard input}:5
\#1 0x000017e3c15e5d7a in *_libc_mmap (addr=Variable "addr" is not available.) at /usr/src/lib/libc/sys/mmap.c:47
\#2 0x000017e17d9abc8b in alloc_code_gen_buffer () at /usr/src/qemu/accel/tcg/translate-all.c:1064
\#3 0x000017e17d9abd04 in code_gen_alloc (tb_size=0) at /usr/src/qemu/accel/tcg/translate-all.c:1112
\#4 0x000017e17d9abe81 in tcg_exec_init (tb_size=0) at /usr/src/qemu/accel/tcg/translate-all.c:1149
\#5 0x000017e17d9897e9 in tcg_init (ms=0x17e45e456800) at /usr/src/qemu/accel/tcg/tcg-all.c:66
\#6 0x000017e17d9891b8 in accel_init_machine (acc=0x17e3c3f50800, ms=0x17e45e456800) at /usr/src/qemu/accel/accel.c:63
\#7 0x000017e17d989312 in configure_accelerator (ms=0x17e45e456800, progname=0x7f7fffff07b0 "lm32-softmmu/qemu-system-lm32") at /usr/src/qemu/accel/accel.c:111
\#8 0x000017e17d9d8616 in main (argc=1, argv=0x7f7fffff06b8, envp=0x7f7fffff06c8) at vl.c:4325

[1] https://www.openbsd.org/faq/upgrade60.html
[2] https://undeadly.org/cgi?action=article&sid=20160527203200

Backports commit 7776ea6b49873ed18a2111e25ed8a6d94bd73db8 from qemu
2019-03-11 16:46:52 -04:00
Luwei Kang
9f2ce63414
i386: extended the cpuid_level when Intel PT is enabled
Intel Processor Trace required CPUID[0x14] but the cpuid_level
have no change when create a kvm guest with
e.g. "-cpu qemu64,+intel-pt

Backports relevant bits of commit
f24c3a79a415042f6dc195f029a2ba7247d14cac from qemu
2019-03-11 16:40:23 -04:00
Lioncash
d6b706a296
qemu/fpu: Synchronize with Qemu
Resolves a few formatting discrepancies
2019-03-09 18:27:31 -05:00
Lioncash
b6f752970b
target/riscv: Initial introduction of the RISC-V target
This ports over the RISC-V architecture from Qemu. This is currently a
very barebones transition. No code hooking or any fancy stuff.
Currently, you can feed it instructions and query the CPU state itself.

This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit
is desirable through Unicorn's interface as well.

Extremely basic examples of executing a single instruction have been
added to the samples directory to help demonstrate how to use the basic
functionality.
2019-03-08 21:46:10 -05:00
Jonas
d27ad4df1b
Added x86Msr functions for the go bindings (#986)
Backports commit d6d413187324e8d9dc852f62016863a44b240a7e from unicorn.
2019-03-08 02:28:37 -05:00
Nguyen Anh Quynh
7cad644235
bindings: update for latest ARM registers addition
Backports commit 07cafff76a3093376755e61124124f6f593d64c9 from unicorn
2019-03-08 02:27:24 -05:00
yhql
1723cb1015
Add ARM MSP, PSP and CONTROL register access (#1071)
Necessary for NVIC exception emulation from user.

Backports commit 31851280316d37305f412fff42f45bb375999074 from unicorn
2019-03-08 02:24:49 -05:00
Lioncash
8f688748c4
translate/i386: Restore Qemu's ordering of CPU and cache definitions
Like the previous two changes, this restores the layout of Qemu's
designated initializers.
2019-03-08 01:51:27 -05:00
Lioncash
1ddbb253e2
target/mips: Restore Qemu's organization of CPU definitions
Like 5075a0158a, this restores Qemu's
formatting of the processor tables to make it significantly less
annoying to maintain.
2019-03-08 01:40:50 -05:00
Lioncash
5075a0158a
target/arm: Restore Qemu's organization of coprocessor registers
These changes were mostly made in upstream unicorn for what I can guess,
was to support old versions of MSVC's compiler.

This is also a pain to maintain, since everything needs to be done
manually and can be a source of errors. It also makes it take more work
than it needs to, to backport changes from qemu.

Because of that, this change restores Qemu's organization of the
coprocessor registers.
2019-03-08 01:32:47 -05:00
Richard Henderson
f116560d2c
target/arm: Implement ARMv8.5-FRINT
Backports 6bea25631af92531027d3bf3ef972a4d51d62e7c from qemu.
2019-03-05 23:17:33 -05:00
Richard Henderson
f855ac073d
target/arm: Restructure handle_fp_1src_{single, double}
This will allow sharing code that adjusts rmode beyond
the existing users.

Backports commit 0e4db23d1fdbfed4fc1ec19b6e59820209600358 from qemu
2019-03-05 23:09:48 -05:00
Richard Henderson
94b5aab8f8
target/arm: Implement ARMv8.5-CondM
Backports commit 5ef84f111483e3f7b57efc690e22081ca8f99544 from qemu
2019-03-05 23:04:06 -05:00
Richard Henderson
1dfa15a683
target/arm: Implement ARMv8.4-CondM
Backports commit b89d9c988a988d5547c73e2bc43f59b0c07420a5 from qemu
2019-03-05 22:59:51 -05:00
Richard Henderson
65a3f3be5b
target/arm: Rearrange disas_data_proc_reg
This decoding more closely matches the ARMv8.4 Table C4-6,
Encoding table for Data Processing - Register Group.

In particular, op2 == 0 is now more than just Add/sub (with carry).

Backports commit 2fba34f70d9a81bab56e61bb99a4d6632bdfe531 from qemu
2019-03-05 22:55:27 -05:00
Richard Henderson
45c297c99b
target/arm: Add set/clear_pstate_bits, share gen_ss_advance
We do not need an out-of-line helper for manipulating bits in pstate.
While changing things, share the implementation of gen_ss_advance.

Backports commit 22ac3c49641f6eed93dca5b852030b4d3eacf6c4 from qemu
2019-03-05 22:55:22 -05:00
Richard Henderson
60742608f5
target/arm: Split helper_msr_i_pstate into 3
The EL0+UMA check is unique to DAIF. While SPSel had avoided the
check by nature of already checking EL >= 1, the other post v8.0
extensions to MSR (imm) allow EL0 and do not require UMA. Avoid
the unconditional write to pc and use raise_exception_ra to unwind.

Backports commit ff730e9666a716b669ac4a8ca7c521177d1d2b15 from qemu
2019-03-05 22:45:11 -05:00
Richard Henderson
5d42ca6a65
target/arm: Implement ARMv8.0-PredInv
Backports commit cb570bd318beb2ecce83cabf8016dacceb824dce from qemu
2019-03-05 22:37:57 -05:00
Richard Henderson
1721e429c2
target/arm: Implement ARMv8.0-SB
Backports commit 9888bd1e20425dfe4dcca5dcd1ca2fac8e90ad19 from qemu
2019-03-05 22:35:16 -05:00
Richard Henderson
a552a7b2e0
target/arm: Split out arm_sctlr
Minimize the number of places that will need updating when
the virtual host extensions are added.

Backports commit 64e40755cd41fbe8cd266cf387e42ddc57a449ef from qemu
2019-03-05 22:29:25 -05:00
Richard Henderson
fa70a2bc69
target/arm: Fix PC test for LDM (exception return)
Found by inspection: Rn is the base register against which the
load began; I is the register within the mask being processed.
The exception return should of course be processed from the loaded PC.

Backports commit 9d090d17234058f55c3c439d285db78c94d7d4de from qemu
2019-03-05 22:27:38 -05:00
Lioncash
7a6f61057b
target/m68k: Correct instruction emulation
Previously we weren't even initializing the instruction table, so any
attempt at emulation would cause a segmentation fault.

This also moves the end address check after the decoding to correctly
perform exiting behavior with the new translator model.
2019-02-28 19:21:49 -05:00
Lioncash
0868015992
target/arm: Move TCGContext variable within arm_post_translate_insn into a narrower scope
This is only used within the scope of the if statement, so we can just
move it there.
2019-02-28 18:53:33 -05:00
Lioncash
15440a83c5
target/arm: Fix execution of ARM instructions
Previously we'd be checking prior to the actual decoding if we were at
the ending address. This worked fine using the old model of the
translation process in qemu. However, this causes the wrong behavior to
occur in both ARM and Thumb/Thumb-2 modes using the newer translator
model.

Given the translator itself checks for the end address already, this
needs to be placed within arm_post_translate_insn().

This prevents the emulation process being off-by-one as well when it
comes to actually executing the instructions.
2019-02-28 18:49:22 -05:00
Lioncash
dcc9420555
Add missing x86_vec regression test
This was initially supposed to be bundled with the changes in the
backported commit: 5bf6d77e4ee258c67c2d7ead94cf266a7b9773e7
2019-02-28 17:08:19 -05:00
dmarxn
7164ab5ff4
changed cpu_compue_eflags to use the updated eflags variable. Otherwise, cli/sti and popfl may break, as we get the non-updated eflags (#1057)
Backports commit 360e9c60e1feb4a93e7e43f30858e38eac2d35f2 from unicorn
2019-02-28 17:05:13 -05:00
nanoric
245d2070fe
[Fix] Add feature support for CMPXCHG16B instruction. (#983)
Backports commit 2a240079d8fa4f1c77208379338c676ac6bf18ce from unicorn
2019-02-28 17:03:08 -05:00
Guillaume Sottas
b7628f215c
fix invalid script path (#975) (#976)
* fix invalid script path (#975)

* expose target_page_align and target_page_size to public API.

* add newly exposed values to python binding.

* Revert "expose target_page_align and target_page_size to public API."

This reverts commit 38145bbaba26900118809c6179164d060b8e73e5.

* Revert "add newly exposed values to python binding."

This reverts commit 0884e06527155799494138733557adaf2f4fe71c.

* add python2-setuptools in required cygwin packages.

* Revert "fix invalid script path (#975)"

This reverts commit 8c55ca7d3447824fb672ab83ff4af5aee9ec089d

Backports commit cf0bcb82b465ec521235ba819a8eba5c46748ddd from unicorn
2019-02-28 17:02:06 -05:00
Disconnect3d
68e17c03dc
Fix naming in Python sample_x86.py (#961)
Backports commit 19ffa83d4353af8834c4c55590ca2ecd357a6bbe from unicorn.
2019-02-28 17:01:10 -05:00
Duncan Ogilvie
8bbe074251
Update dotnet bindings (#973)
Backports commit 0b3cd70e67ef8cd564e86f502a411d4e98b9f752 from unicorn.
2019-02-28 17:00:25 -05:00
Jeremy Sears
c3c6e250e4
Fix Java Makefile on Darwin (#936)
* Fixes the logic for Dylib extensions on macOS.
* Adds an uninstall task and documentation.

Backports commit 94b116877670ed9bbe38b71e3b9ad28f10cb3775 from unicorn
2019-02-28 16:58:03 -05:00
Brian McKenna
07f315af47
Haskell bindings: use ExceptT instead of deprecated EitherT (#1034)
Backports commit 873fffc505b29c6179a8aece18b7e331e5f879e8 from unicorn.
2019-02-28 16:54:02 -05:00
nanoric
9e8e5645fc
[Fix] Fix a problem that use uc_reg_write to write fs, gs has no effets in x86 64-bit mode. (#984)
Backports commit a2493a0d4121b671fe9d16e41a9bdd3307b7b1ef from unicorn.
2019-02-28 16:52:54 -05:00
BrunoPujos
1d4bfd9aca
i386: set MSR IA32_EFER to correct value at init for IA32e Mode (#1047)
Backports commit 536c4e77c4350fac3e5c2b9b57d8c16f69b934d3 from unicorn.
2019-02-28 16:49:31 -05:00
Diego Argueta
50a570e126
Add Lua binding to README (#1050)
Closes https://github.com/dargueta/unicorn-lua/issues/1

Backports commit f2438188069e31d637666e72dcddd13cef0e684e from qemu
2019-02-28 16:48:20 -05:00
kj.xwings.l
15d52aefbe
update python binding samples, shellcode.py with 64bit syscall (#1052)
* update python binding samples, shellcode.py with 64bit syscall

* fix with quynh comments

* fix with more q comments

* reformatted

* reformatted and moved file

* reformatted and moved file

* delete file

* delete dead code

* deleted more dead code

* deleted more dead code / fix bugs

* fix 64bit eip intno eax

* rearrage rip

* Inconsistent print

Backports commit 8c6cbe3f3cabed57b23b721c29f937dd5baafc90 from unicorn.
2019-02-28 16:47:23 -05:00
Nguyen Anh Quynh
7bb8554242
bindings: update after recent addition of ARM_REG_IPSR
Backports 6d47b38b7f8b6de0ee96a93a91180fafe2f01525 from unicorn
2019-02-28 16:44:43 -05:00