Commit Graph

3372 Commits

Author SHA1 Message Date
Lioncash
a59eef391e
atomic: MSVC compatible equivalents to some functions 2018-02-27 10:56:04 -05:00
Emilio G. Cota
c837d76a86
atomics: add atomic_op_fetch variants
This paves the way for upcoming work.

Backports commit 83d0c719f837724d9e3963b078211b2242bdd2a5 from qemu
2018-02-27 10:28:27 -05:00
Emilio G. Cota
102a53aa50
atomics: add atomic_xor
This paves the way for upcoming work.

Backports commit 61696ddbdc74263ddb6869856772cfe355a5d3bd from qemu
2018-02-27 10:23:31 -05:00
Richard Henderson
3fe8d46a15
atomics: Add parameters to macros
Making these functional rather than object macros will
prevent later problems with complex macro expansion.

Backports commit d1a9f2d12fcfc942924956fbe321aedf4226ccb7 from qemu
2018-02-27 10:21:35 -05:00
Richard Henderson
4168095fed
target-m68k: Optimize gen_flush_flags
Backports commit 36f0399d46f2ccf4f6e7451ba46b1e8d0e9ab341 from qemu
2018-02-27 10:19:54 -05:00
Richard Henderson
7403e63f2f
target-m68k: Optimize some comparisons
Backports commit 9d896621c1820fd8f437fac26fd7d2e0921091c3 from qemu
2018-02-27 10:15:20 -05:00
Richard Henderson
672a28173f
target-m68k: Use setcond for scc
Backports commit b459e3eccfae7fe83e30187c391de00bccf4f51d from qemu
2018-02-27 10:11:35 -05:00
Richard Henderson
ed6feb9329
target-m68k: Introduce DisasCompare
Backports commit 6a432295d73df91890dc70c4a94dcc4ba88ad1c3 from qemu
2018-02-27 10:08:32 -05:00
Richard Henderson
4e498cc54d
target-m68k: Reorg flags handling
Separate all ccr bits. Continue to batch updates via cc_op.

Backports commit 620c6cf66584bfbee90db84a7e87a6eabf230ca9 from qemu
2018-02-27 10:02:02 -05:00
Richard Henderson
121309a4d0
target-m68k: Reorg flags handling
Separate all ccr bits. Continue to batch updates via cc_op.

Signed-off-by: Richard Henderson <rth@twiddle.net>

Fix gen_logic_cc() to really extend the size of the result.
Fix gen_get_ccr(): update cc_op as it is used by the helper.
Factorize flags computing and src/ccr cleanup

Backports commit 620c6cf66584bfbee90db84a7e87a6eabf230ca9 from qemu
2018-02-27 09:30:32 -05:00
Richard Henderson
61ab9a42cd
target-m68k: Remove incorrect clearing of cc_x
The CF docs certainly doesnt suggest this is true.

Backports commit 18dd87f26bed46f22bb1b9536329c02de500f407 from qemu
2018-02-27 09:21:26 -05:00
Richard Henderson
187c2a9807
target-m68k: Some fixes to SR and flags management
Backports commit 99c514485b1d7922c4ca1ed767fd45525de4701f from qemu
2018-02-27 09:19:21 -05:00
Richard Henderson
9493b29399
target-m68k: Print flags properly
Backports commit 8e394ccabdb1e439aab092de6b9d2f26432e962f from qemu
2018-02-27 09:17:44 -05:00
Laurent Vivier
57ea90a91f
target-m68k: update CPU flags management
Copied from target-i386

Backports commit 9fdb533fb129b19610941bd1e5dd93e7471a18f5 from qemu
2018-02-27 09:15:29 -05:00
Laurent Vivier
125675e334
target-m68k: don't update cc_dest in helpers
Backports commit 91f90d7191f862ab27528dbdf76cee55c77f79cf from qemu
2018-02-27 09:04:51 -05:00
Laurent Vivier
12f9ba3fe4
target-m68k: update move to/from ccr/sr
Backports commit 7c0eb318bdcc3667a861e7b0f140df0b6d9895e2 from qemu
2018-02-27 08:57:05 -05:00
Laurent Vivier
b8366d5b31
target-m68k: remove m68k_cpu_exec_enter() and m68k_cpu_exec_exit()
Update cc_op directly from tcg_gen_insn_start() and
restore_state_to_opc()

Copied from target-i386

Backports commit 20a8856eba0980fbe9d2b8ed2b33ecdb9c9fe5ad from qemu
2018-02-27 08:53:02 -05:00
Laurent Vivier
a521f4f41d
target-m68k: Replace helper_xflag_lt with setcond
Backports commit f9083519034aaa5ad5cd2c5727bd61c29bf60bc5 from qemu
2018-02-27 08:50:44 -05:00
Laurent Vivier
b079255576
target-m68k: allow to update flags with operation on words and bytes
Backports commit 5dbb6784b7e2b833c036b4df58aa07067e35f476 from qemu
2018-02-27 08:47:12 -05:00
Laurent Vivier
f069762b61
target-m68k: REG() macro cleanup
Backports commit bcc098b0c23b4dd902ff56987d769bd839677331 from qemu
2018-02-27 08:37:25 -05:00
Laurent Vivier
3d59fe56b3
target-m68k: set PAGE_BITS to 12 for m68k
Backports commit 2b04e85a3401e13cb19b1de197e6c211eaadca4c from qemu
2018-02-27 08:36:09 -05:00
Laurent Vivier
292fc83c86
target-m68k: define operand sizes
Backports commit 7ef25cdd6cee4fa468d6cb913fa064a6689faf7d from qemu
2018-02-27 08:35:13 -05:00
Laurent Vivier
2653165c63
target-m68k: introduce read_imXX() functions
Read a 8, 16 or 32bit immediat constant.

An immediate constant is stored in the instruction opcode and
can be in one or two extension words.

Backports commit 28b68cd79ef01e8b1f5bd26718cd8c09a12c625f from qemu
2018-02-27 08:32:04 -05:00
Laurent Vivier
d29cbb70b3
target-m68k: manage scaled index
Scaled index is not supported by 68000, 68008, and 68010.

EA = (bd + PC) + Xn.SIZE*SCALE + od

Ignore it:

M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
2.4 BRIEF EXTENSION WORD FORMAT COMPATIBILITY

"If the MC68000 were to execute an instruction that
encoded a scaling factor, the scaling factor would be
ignored and would not access the desired memory address.
The earlier microprocessors do not recognize the brief
extension word formats implemented by newer processors.
Although they can detect illegal instructions, they do not
decode invalid encodings of the brief extension word formats
as exceptions."

Backports commit d8633620a112296fcf6a6ae9a1cbba614c0ca502 from qemu
2018-02-27 08:27:20 -05:00
Laurent Vivier
fa4a71a1bf
target-m68k: define m680x0 CPUs and features
This patch defines height new features:

- M68K_FEATURE_SCALED_INDEX, scaled address index register
- M68K_FEATURE_LONG_MULDIV, 32bit multiply/divide
- M68K_FEATURE_QUAD_MULDIV, 64bit multiply/divide
- M68K_FEATURE_BCCL, long conditional branches
- M68K_FEATURE_BITFIELD, bit field instructions
- M68K_FEATURE_FPU, FPU instructions
- M68K_FEATURE_CAS, cas instruction
- M68K_FEATURE_BKPT, bkpt instruction

Backports commit f076803bbf6ad1618f493f543faff97f3dd0c970 from qemu
2018-02-27 08:26:06 -05:00
John Paul Adrian Glaubitz
2fd7779aa5
target-m68k: Build the opcode table only once to avoid multithreading issues
Backports commit b208525797b031c1be4121553e21746686318a38 from qemu
2018-02-27 08:14:35 -05:00
Laurent Vivier
fd84549b3e
target-m68k: fix DEBUG_DISPATCH
Backports commit a1ff19302007986fa081738e88905a715bd68e2e from qemu
2018-02-27 08:07:21 -05:00
Daniel P. Berrange
83a5bf2d25
qapi: rename QmpOutputVisitor to QObjectOutputVisitor
The QmpOutputVisitor has no direct dependency on QMP. It is
valid to use it anywhere that one wants a QObject. Rename it
to better reflect its functionality as a generic QAPI
to QObject converter.

The commit before previous renamed the files, this one renames C
identifiers.

Backports commit 7d5e199ade76c53ec316ab6779800581bb47c50a from qemu
2018-02-27 08:05:33 -05:00
Daniel P. Berrange
2949a90977
qapi: rename QmpInputVisitor to QObjectInputVisitor
The QmpInputVisitor has no direct dependency on QMP. It is
valid to use it anywhere that one has a QObject. Rename it
to better reflect its functionality as a generic QObject
to QAPI converter.

The previous commit renamed the files, this one renames C identifiers.

Backports commit 09e68369a88d7de0f988972bf28eec1b80cc47f9 from qemu
2018-02-26 15:54:15 -05:00
Daniel P. Berrange
228f122248
qapi: rename *qmp-*-visitor* to *qobject-*-visitor*
The QMP visitors have no direct dependency on QMP. It is
valid to use them anywhere that one has a QObject. Rename them
to better reflect their functionality as a generic QObject
to QAPI converter.

This is the first of three parts: rename the files. The next two
parts will rename C identifiers. The split is necessary to make git
rename detection work.

Backports commit b3db211f3c80bb996a704d665fe275619f728bd4 from qemu
2018-02-26 15:42:37 -05:00
Peter Maydell
1a850bcb19
target-arm: Implement new HLT trap for semihosting
Version 2.0 of the semihosting specification introduces new trap
instructions for AArch32: HLT 0xF000 for A32 and HLT 0x3C for T32.
Implement these (in the same way we implement the existing HLT
semihosting trap for A64).

The old traps via SVC and BKPT are unaffected.

Backports commit 19a6e31c9d2701ef648b70ddcfc3bf64cec8c37e from qemu
2018-02-26 15:28:45 -05:00
Peter Maydell
db8b0a82b1
cpu: Support a target CPU having a variable page size
Support target CPUs having a page size which isn't knownn
at compile time. To use this, the CPU implementation should:
* define TARGET_PAGE_BITS_VARY
* not define TARGET_PAGE_BITS
* define TARGET_PAGE_BITS_MIN to the smallest value it
might possibly want for TARGET_PAGE_BITS
* call set_preferred_target_page_bits() in its realize
function to indicate the actual preferred target page
size for the CPU (and report any error from it)

In CONFIG_USER_ONLY, the CPU implementation should continue
to define TARGET_PAGE_BITS appropriately for the guest
OS page size.

Machines which want to take advantage of having the page
size something larger than TARGET_PAGE_BITS_MIN must
set the MachineClass minimum_page_bits field to a value
which they guarantee will be no greater than the preferred
page size for any CPU they create.

Note that changing the target page size by setting
minimum_page_bits is a migration compatibility break
for that machine.

For debugging purposes, attempts to use TARGET_PAGE_SIZE
before it has been finally confirmed will assert.

Backports commit 20bccb82ff3ea09bcb7c4ee226d3160cab15f7da from qemu
2018-02-26 12:29:08 -05:00
Vijaya Kumar K
a7229cc08a
translate-all.c: Compute L1 page table properties at runtime
Remove L1 page mapping table properties computing
statically using macros which is dependent on
TARGET_PAGE_BITS. Drop macros V_L1_SIZE, V_L1_SHIFT,
V_L1_BITS macros and replace with variables which are
computed at early stage of VM boot.

Removing dependency can help to make TARGET_PAGE_BITS
dynamic.

Backports commit 66ec9f49399f0a9fa13ee77c472caba0de2773fc from qemu
2018-02-26 11:46:58 -05:00
Vijaya Kumar K
3082b4e4ec
exec.c: Remove static allocation of sub_section of sub_page
Allocate sub_section dynamically. Remove dependency
on TARGET_PAGE_SIZE to make run-time page size detection
for arm platforms.

Backports commit 2615fabd42ea0078dd9e659bdb21a5b7a1f87a9a from qemu
2018-02-26 10:50:04 -05:00
Paolo Bonzini
eb75004013
memory: add a per-AddressSpace list of listeners
This speeds up MEMORY_LISTENER_CALL noticeably. Right now,
with many PCI devices you have N regions added to M AddressSpaces
(M = # PCI devices with bus-master enabled) and each call looks
up the whole listener list, with at least M listeners in it.
Because most of the regions in N are BARs, which are also roughly
proportional to M, the whole thing is O(M^3). This changes it
to O(M^2), which is the best we can do without rewriting the
whole thing.

Backports commit 9a54635dcb51a3fcf7507af630168f514a8cd4e7 from qemu
2018-02-26 10:46:50 -05:00
Paolo Bonzini
4b06e8bbb7
memory: eliminate global MemoryListeners
There is none, so just drop the code.

Backports commit d45fa784cd0c111131696808d1168259d66b7519 from qemu
2018-02-26 10:19:28 -05:00
Paolo Bonzini
8734e13a73
tcg: try sti when moving a constant into a dead memory temp
This comes from free from unifying tcg_reg_alloc_mov and
tcg_reg_alloc_movi's handling of TEMP_VAL_CONST. It triggers
often on moves to cc_dst, such as the following translation
of "sub $0x3c,%esp":

before: after:
subl $0x3c,%ebp subl $0x3c,%ebp
movl %ebp,0x10(%r14) movl %ebp,0x10(%r14)
movl $0x3c,%ebx movl $0x3c,0x2c(%r14)
movl %ebx,0x2c(%r14)

Backports commit 0fe4fca4e1a5e06a270127dd80bb753d4dda61c6 from qemu
2018-02-26 10:08:47 -05:00
Paolo Bonzini
be00a3e100
target-i386: fix 32-bit addresses in LEA
This was found with test-i386. The issue is that instructions
such as

addr32 lea (%eax), %rax

did not perform a 32-bit extension, because the LEA translation
skipped the gen_lea_v_seg step. That step does not just add
segments, it also takes care of extending from address size to
pointer size.

Backports commit 620abfb004543404bef1953e25da2ad77352941a from qemu
2018-02-26 10:06:08 -05:00
Paolo Bonzini
8b239bd48b
atomic: base mb_read/mb_set on load-acquire and store-release
This introduces load-acquire and store-release operations in QEMU.
For now, just use them as an implementation detail of atomic_mb_read
and atomic_mb_set.

Since docs/atomics.txt documents that atomic_mb_read only synchronizes
with an atomic_mb_set of the same variable, we can use the new implementation
everywhere instead of seq-cst loads and stores.

Backports commit 803cf26a9e019b5d2256a8edeb22e3538c4f3261 from qemu
2018-02-26 10:02:46 -05:00
Paolo Bonzini
fd7ef4c184
atomic: introduce smp_mb_acquire and smp_mb_release 2018-02-26 09:58:22 -05:00
Eduardo Habkost
b41bb81737
target-i386: Don't use cpu->migratable when filtering features
When explicitly enabling unmigratable flags using "-cpu host"
(e.g. "-cpu host,+invtsc"), the requested feature won't be
enabled because cpu->migratable is true by default.

This is inconsistent with all other CPU models, which don't have
the "migratable" option, making "+invtsc" work without the need
for extra options.

This happens because x86_cpu_filter_features() uses
cpu->migratable as an argument for
x86_cpu_get_supported_feature_word(). This is not useful
because:
2) on "-cpu host" it only makes QEMU disable features that were
explicitly enabled in the command-line;
1) on all the other CPU models, cpu->migratable is already false.

The fix is to just use 'false' as an argument to
x86_cpu_get_supported_feature_word() in
x86_cpu_filter_features().

Note that:

* This won't change anything for people using using
"-cpu host" or "-cpu host,migratable=<on|off>" (with no extra
features) because the x86_cpu_get_supported_feature_word() call
on the cpu->host_features check uses cpu->migratable as
argument.
* This won't change anything for any CPU model except "host"
because they all have cpu->migratable == false (and only "host"
has the "migratable" property that allows it to be changed).
* This will only change things for people using "-cpu host,+<feature>",
where <feature> is a non-migratable feature. The only existing
named non-migratable feature is "invtsc".

In other words, this change will only affect people using
"-cpu host,+invtsc" (that will now get what they asked for: the
invtsc flag will be enabled). All other use cases are unaffected.

Backports commit 46c032f3afcc05a0123914609f1003906ba63fda from qemu
2018-02-26 09:51:14 -05:00
Eduardo Habkost
4096ce0184
target-i386: x86_cpu_load_features() function
When probing for CPU model information, we need to reuse the code
that initializes CPUID fields, but not the remaining side-effects
of x86_cpu_realizefn(). Move that code to a separate function
that can be reused later.

Backports commit 41f3d4d69a423dadb8431fda65d8d7c68c0de0fc from qemu
2018-02-26 09:49:34 -05:00
Eduardo Habkost
aa98c8a93f
target-i386: Move warning code outside x86_cpu_filter_features()
x86_cpu_filter_features() will be reused by code that shouldn't
print any warning. Move the warning code to a new
x86_cpu_report_filtered_features() function, and call it from
x86_cpu_realizefn().

Backports commit 8ca30e8673aff9bfcf8f969f8db4266b5f62e49c from qemu
2018-02-26 09:40:11 -05:00
Eduardo Habkost
08bfa41e1b
target-i386: xsave: Add FP and SSE bits to x86_ext_save_areas
Instead of treating the FP and SSE bits as special cases, add
them to the x86_ext_save_areas array. This will simplify the code
that calculates the supported xsave components and the size of
the xsave area.

Backports commit e3c9022b4e2b6a4deb6518361d2bbf33522b9198 from qemu
2018-02-26 09:37:48 -05:00
Eduardo Habkost
54bd827472
target-i386: Register properties for feature aliases manually
Instead of keeping the aliases inside the feature name arrays and
require parsing the strings, just register alias properties
manually. This simplifies the code for property registration and
lookup.

Backports commit 16d2fcaa509b1ca56eb2fcd8fe877279cf65cccc from qemu
2018-02-26 09:34:52 -05:00
Eduardo Habkost
b508b9e02a
target-i386: Remove underscores from feat_names arrays
Instead of translating the feature name entries when adding
property names, store the actual property names in the feature
name array.

For reference, here is the full list of functions that use
FeatureWordInfo::feat_names:

* x86_cpu_get_migratable_flags(): not affected, as it just
check for non-NULL values.
* report_unavailable_features(): informative only. It will
start printing feature names with hyphens.
* x86_cpu_list(): informative only. It will start printing
feature names with hyphens
* x86_cpu_register_feature_bit_props(): not affected, as it
was already calling feat2prop(). Now we can remove the
feat2prop() calls safely.

So, the only user-visible effect of this patch are the new names
being used in help and error messages for users.

Backports commit fc7dfd205f3287893c436d932a167bffa30579c8 from qemu
2018-02-26 09:33:15 -05:00
Eduardo Habkost
6d1a7bccb5
target-i386: Disable VME by default with TCG
VME is already disabled automatically when using TCG. So, instead
of pretending it is there when reporting CPU model data on
query-cpu-* QMP commands (making every CPU model to be reported
as not runnable), we can disable it by default on all CPU models
when using TCG.

Do that by adding a tcg_default_props array that will work like
kvm_default_props.

Backports commit 04d99c3c61f4bdc0450dbeb6512b6dd743baca65 from qemu
2018-02-26 08:23:44 -05:00
Eduardo Habkost
594cbeaa06
target-i386: List CPU models using subclass list
Instead of using the builtin_x86_defs array, use the QOM subclass
list to list CPU models on "-cpu ?" and "query-cpu-definitions".

Backports commit ee465a3ef77c2b2975ffa71c72208c05b3f3970d from qemu
2018-02-26 08:17:04 -05:00
Peter Maydell
200771d0ba
target-arm: Add trace events for the generic timers
Backports commit 194cbc492bcc8f3f1868ec97a35146bc99c3c71c from qemu
2018-02-26 08:15:42 -05:00
Peter Maydell
158bfc109a
target-arm: Implement dummy MDCCINT_EL1
MDCCINT_EL1 is part of the DCC debugger communication
channel between the CPU and an attached external debugger.
QEMU doesn't implement this, but since Linux may try
to access this register we need to provide at least
a dummy implementation.

Backports commit 5dbdc4342f479d799a1970dd5fd22e64c9dcd50d from qemu
2018-02-26 08:11:54 -05:00