Commit Graph

2226 Commits

Author SHA1 Message Date
Paolo Bonzini
5e9ea14b7e
target-i386: add feature flags for CPUID[EAX=0xd,ECX=1]
These represent xsave-related capabilities of the processor, and KVM may
or may not support them.

Add feature bits so that they are considered by "-cpu ...,enforce", and use
the new feature work instead of calling kvm_arch_get_supported_cpuid.

Bit 3 (XSAVES) is not migratables because it requires saving MSR_IA32_XSS.
Neither KVM nor any commonly available hardware supports it anyway.

Backports commit 0bb0b2d2fe7f645ddaf1f0ff40ac669c9feb4aa1 from qemu

also backports 18cd2c17b5370369a886155c001da0a7f54bbcca
2018-02-17 15:23:19 -05:00
Eduardo Habkost
a439a8c701
qom: strdup() target property name on object_property_add_alias()
With this, object_property_add_alias() callers can safely free the
target property name, like what already happens with the 'name' argument
to all object_property_add*() functions.

Backports commit 1590d266d96b3f9b42443d6388dfc38f527ac2d8 from qemu
2018-02-17 15:23:19 -05:00
Peter Maydell
484a9cc21b
target-arm: Fix broken SCTLR_EL3 reset
The SCTLR_EL3 cpreg definition was implicitly resetting the
register state to 0, which is both wrong and clashes with
the reset done via the SCTLR definition (since sctlr[3]
is unioned with sctlr_s). This went unnoticed until recently,
when an unrelated change (commit a903c449b41f105aa) happened to
perturb the order of enumeration through the cpregs hashtable for
reset such that the erroneous reset happened after the correct one
rather than before it. Fix this by marking SCTLR_EL3 as an alias,
so its reset is left up to the AArch32 view.

Backports commit e46e1a74ef482f1ef773e750df9654ef4442ca29 from qemu
2018-02-17 15:23:19 -05:00
Peter Crosthwaite
6279dfc113
cpu: Add wrapper for the set_pc() hook
Add a wrapper around the CPUClass::set_pc() hook.

Backports commit 2991b8904730d663f12ad42e35798ecc22fe151c from qemu
2018-02-17 15:23:19 -05:00
Peter Crosthwaite
e51f8c9f6f
cpu-exec: Purge all uses of ENV_GET_CPU()
Remove un-needed usages of ENV_GET_CPU() by converting the APIs to use
CPUState pointers and retrieving the env_ptr as minimally needed.

Scripted conversion for target-* change:

for I in target-*/cpu.h; do
sed -i \
's/\(^int cpu_[^_]*_exec(\)[^ ][^ ]* \*s);$/\1CPUState *cpu);/' \
$I;
done

Backports commit ea3e9847408131abc840240bd61e892d28459452 from qemu
2018-02-17 15:23:18 -05:00
Peter Crosthwaite
9e23308b66
cpu: Change cpu_exec_init() arg to cpu, not env
The callers (most of them in target-foo/cpu.c) to this function all
have the cpu pointer handy. Just pass it to avoid an ENV_GET_CPU() from
core code (in exec.c).

Backports commit 4bad9e392e788a218967167a38ce2ae7a32a6231 from qemu
2018-02-17 15:23:18 -05:00
Peter Crosthwaite
50b6fa93a8
cpu: Change tcg_cpu_exec() arg to cpu, not env
The sole caller of this function navigates the cpu->env_ptr only for
this function to take it back the cpu pointer straight away. Pass in
cpu pointer instead and grab the env pointer locally in the function.
Removes a core code usage of ENV_GET_CPU().

Backports commit 3d57f7893c90d911d786cb2c622b0926fc808b57 from qemu
2018-02-17 15:23:18 -05:00
Peter Crosthwaite
8200453545
translate-all: Change tb_flush() env argument to cpu
All of the core-code usages of this API have the cpu pointer handy so
pass it in. There are only 3 architecture specific usages (2 of which
are commented out) which can just use ENV_GET_CPU() locally to get the
cpu pointer. The reduces core code usage of the CPU env, which brings
us closer to common-obj'ing these core files.

Backports commit bbd77c180d7ff1b04a7661bb878939b2e1d23798 from qemu
2018-02-17 15:23:18 -05:00
Eduardo Habkost
79c95aa18b
cpu: Initialize breakpoint/watchpoint lists in cpu_common_initfn()
One small step in the simplification of cpu_exec_init().

Backports commit 7c39163e389e6e6e16965606fb5a26abcdb6ad73 from qemu
2018-02-17 15:23:18 -05:00
Eduardo Habkost
4e39fabd4d
cpu: No need to zero-initialize CPUState::numa_node
QOM objects are already zero-filled when instantiated, there's no need
to explicitly set numa_node to 0.

Backports commit 199fc85acd0571902eeefef6ea861b8ba4c8201f from qemu
2018-02-17 15:23:18 -05:00
Daniel P. Berrange
2e97ecfbcd
crypto: move built-in AES implementation into crypto/
To prepare for a generic internal cipher API, move the
built-in AES implementation into the crypto/ directory

Backports commit 6f2945cde60545aae7f31ab9d5ef29531efbc94f from qemu
2018-02-17 15:23:17 -05:00
Daniel P. Berrange
5019f39c15
crypto: introduce new module for computing hash digests
Introduce a new crypto/ directory that will (eventually) contain
all the cryptographic related code. This initially defines a
wrapper for initializing gnutls and for computing hashes with
gnutls. The former ensures that gnutls is guaranteed to be
initialized exactly once in QEMU regardless of CLI args. The
block quorum code currently fails to initialize gnutls so it
only works by luck, if VNC server TLS is not requested. The
hash APIs avoids the need to litter the rest of the code with
preprocessor checks and simplifies callers by allocating the
correct amount of memory for the requested hash.

Backports commit ddbb0d09661f5fce21b335ba9aea8202d189b98e from qemu
2018-02-17 15:23:17 -05:00
Aurelien Jarno
ba73fd9162
tcg/s390: fix branch target change during code retranslation
Make sure to not modify the branch target. This ensure that the
branch target is not corrupted during partial retranslation.

Backports commit cd3b29b745b0ff393b2d37317837bc726b8dacc8 from qemu
2018-02-17 15:23:17 -05:00
Paolo Bonzini
fa2b872b0b
target-i386: avoid overflow in the tsc-frequency property
The TSC frequency fits comfortably in an int when expressed in kHz,
but it may overflow when converted to Hz. In this case,
tsc-frequency returns a negative value because x86_cpuid_get_tsc_freq
does a 32-bit multiplication before assigning to int64_t.

For simplicity just make tsc_khz a 64-bit value.

Backports commit 06ef227e5158cca6710e6c268d6a7f65a5e2811b from qemu
2018-02-17 15:23:17 -05:00
Peter Crosthwaite
13b919f5c8
cpu-all: complete real host page size API
Currently the "host" page size alignment API is really aligning to both
host and target page sizes. There is the qemu_real_page_size which can
be used for the actual host page size but it's missing a mask and ALIGN
macro as provided for qemu_page_size. Complete the API. This allows
system level code that cares about the host page size to use a
consistent alignment interface without having to un-needingly align to
the target page size. This also reduces system level code dependency
on the cpu specific TARGET_PAGE_SIZE.

Backports commit 4e51361d79289aee2985dfed472f8d87bd53a8df from qemu
2018-02-17 15:23:16 -05:00
Paolo Bonzini
6153671333
target-i386: add support for SMBASE MSR and SMIs
Apart from the MSR, the smi field of struct kvm_vcpu_events has to be
translated into the corresponding CPUX86State fields. Also,
memory transaction flags depend on SMM state, so pull it from struct
kvm_run on every exit from KVM to userspace.

Backports relevant parts of commit fc12d72e10828ca6ff75f2ad432b741f07a10cef from qemu
2018-02-17 15:23:16 -05:00
Paolo Bonzini
a6ea34ee0c
exec: skip MMIO regions correctly in cpu_physical_memory_write_rom_internal
Loading the BIOS in the mac99 machine is interesting, because there is a
PROM in the middle of the BIOS region (from 16K to 32K). Before memory
region accesses were clamped, when QEMU was asked to load a BIOS from
0xfff00000 to 0xffffffff it would put even those 16K from the BIOS file
into the region. This is weird because those 16K were not actually
visible between 0xfff04000 and 0xfff07fff. However, it worked.

After clamping was added, this also worked. In this case, the
cpu_physical_memory_write_rom_internal function split the write in
three parts: the first 16K were copied, the PROM area (second 16K) were
ignored, then the rest was copied.

Problems then started with commit 965eb2f (exec: do not clamp accesses
to MMIO regions, 2015-06-17). Clamping accesses is not done for MMIO
regions because they can overlap wildly, and MMIO registers can be
expected to perform full-width accesses based only on their address
(with no respect for adjacent registers that could decode to completely
different MemoryRegions). However, this lack of clamping also applied
to the PROM area! cpu_physical_memory_write_rom_internal thus failed
to copy the third range above, i.e. only copied the first 16K of the BIOS.

In effect, address_space_translate is expecting _something else_ to do
the clamping for MMIO regions if the incoming length is large. This
"something else" is memory_access_size in the case of address_space_rw,
so use the same logic in cpu_physical_memory_write_rom_internal.

Backports commit b242e0e0e2969c044a318e56f7988bbd84de1f63 from qemu
2018-02-17 15:23:16 -05:00
Peter Maydell
2f3f2ae092
Stop including qemu-common.h in memory.h
Including qemu-common.h from other header files is generally a bad
idea, because it means it's very easy to end up with a circular
dependency. For instance, if we wanted to include memory.h from
qom/cpu.h we'd end up with this loop:
memory.h -> qemu-common.h -> cpu.h -> cpu-qom.h -> qom/cpu.h -> memory.h

Remove the include from memory.h. This requires us to fix up a few
other files which were inadvertently getting declarations indirectly
through memory.h.

The biggest change is splitting the fprintf_function typedef out
into its own header so other headers can get at it without having
to include qemu-common.h.

Backports commit fba0a593b2809ecdda68650952cf3d3332ac1990 from qemu
2018-02-17 15:23:16 -05:00
Jan Kiszka
b93c24ba31
memory: Add global-locking property to memory regions
This introduces the memory region property "global_locking". It is true
by default. By setting it to false, a device model can request BQL-free
dispatching of region accesses to its r/w handlers. The actual BQL
break-up will be provided in a separate patch.

Backports commit 196ea13104f802c508e57180b2a0d2b3418989a3 from qemu
2018-02-17 15:23:16 -05:00
Peter Crosthwaite
92cd41d78e
memory_mapping: Rework cpu related includes
This makes it more consistent with all other core code files, which
either just rely on qemu-common.h inclusion or precede cpu.h with
qemu-common.h.

cpu-all.h should not be included in addition to cpu.h. Remove it.

Backports commit 94beb661bd90bcb477eed6d3b07aced988c40163 from qemu
2018-02-17 15:23:15 -05:00
Peter Crosthwaite
82a22d8f3a
cpu-defs: Move out TB_JMP defines
These are not Architecture specific in any way so move them out of
cpu-defs.h. tb-hash.h is an appropriate place as a leading user and
their strong relationship to TB hashing and caching.

Backports commit 41da4bd6420afd1209c408974920f63ff9c658e1 from qemu
2018-02-17 15:23:15 -05:00
Peter Crosthwaite
09d23c6604
include/exec: Move tb hash functions out
This is one of very few things in exec-all with a genuine CPU
architecture dependency. Move these hashing helpers to a new
header to trim exec-all.h down to a near architecture-agnostic
header.

The defs are only used by cpu-exec and translate-all which are both
arch-obj's so the new tb-hash.h has no core code usage.

Backports commit e1b89321bafea9fb33d87852fc91fee579d17dfe from qemu
2018-02-17 15:23:15 -05:00
Peter Crosthwaite
860e4184df
include/exec: Move standard exceptions to cpu-all.h
These exception indicies are generic and don't have any reliance on the
per-arch cpu.h defs. Move them to cpu-all.h so they can be used by core
code that does not have access to cpu-defs.h.

Backports commit 9e0dc48c9f05505b53cb28f860456a0648e56ddf from qemu
2018-02-17 15:23:15 -05:00
Artyom Tarasenko
e1b179a7d3
qemu-common: add VEC_OR macro
Intel C Compiler version 15.0.3.187 Build 20150407 doesn't support
'|' function for non floating-point simd operands.

Define VEC_OR macro which uses _mm_or_si128 supported
both in icc and gcc on x86 platform.

Backports commit 34664507c7f038842f20a2c787915680b1fabba2 from qemu
2018-02-17 15:23:15 -05:00
Peter Crosthwaite
a591219ad6
cpu-defs: Move CPU_TEMP_BUF_NLONGS to tcg
The usages of this define are pure TCG and there is no architecture
specific variation of the value. Localise it to the TCG engine to
remove another architecture agnostic piece from cpu-defs.h.

This follows on from a28177820a868eafda8fab007561cc19f41941f4 where
temp_buf was moved out of the CPU_COMMON obsoleting the need for
the super early definition.

Backports commit 6e0b07306d1793e8402dd218d2e38a7377b5fc27 from qemu
2018-02-17 15:23:15 -05:00
Peter Maydell
5c7389680e
target-arm: Implement YIELD insn to yield in ARM and Thumb translators
Implement the YIELD instruction in the ARM and Thumb translators to
actually yield control back to the top level loop rather than being
a simple no-op. (We already do this for A64.)

Backports commit c87e5a61c2b3024116f52f7e68273f864ff7ab82 from qemu
2018-02-17 15:23:14 -05:00
Peter Maydell
8840d8370d
target-arm: Split DISAS_YIELD from DISAS_WFE
Currently we use DISAS_WFE for both WFE and YIELD instructions.
This is functionally correct because at the moment both of them
are implemented as "yield this CPU back to the top level loop so
another CPU has a chance to run". However it's rather confusing
that YIELD ends up calling HELPER(wfe), and if we ever want to
implement real behaviour for WFE and SEV it's likely to trip us up.

Split out the yield codepath to use DISAS_YIELD and a new
HELPER(yield) function, and have HELPER(wfe) call HELPER(yield).

Backports commit 049e24a191c212d9468db84169197887f2c91586 from qemu
2018-02-17 15:23:14 -05:00
Sergey Fedorov
bcf57618a8
target-arm: fix write helper for TLBI ALLE1IS
TLBI ALLE1IS is an operation that does invalidate TLB entries on all PEs
in the same Inner Sharable domain, not just on the current CPU. So we
must use tlbiall_is_write() here.

Backports commit 2a6332d968297266dbabf9d33f959e3a5efdd0f9 from qemu
2018-02-17 15:23:14 -05:00
Laurent Vivier
2efa61c249
m68k: remove useless parameter op_size from gen_lea_indexed()
Backports commit a435612616202c837d62626dbe3e33a4e9a95772 from qemu
2018-02-17 15:23:14 -05:00
Laurent Vivier
18e3e405c4
m68k: remove useless file m68k-qreg.h
Unused since:

commit e1f3808e03f73e7a7fa966afbed2455dd052202e

Backports commit bb337ac978b6def085eabf17830d5cc2a1bce6a8 from qemu
2018-02-17 15:23:13 -05:00
Laurent Vivier
12cb26ab6c
m68k: is_mem is useless
Remove is_mem as it is never tested anymore since:

commit bfa50bc2638d877cf2900712b7503be22e8811cb

Backports commit 805167adcb900fa7b2b114d639c418f5313d0b42 from qemu
2018-02-17 15:23:13 -05:00
Soren Brinkmann
fd2ac3058f
target-arm: A64: Print ELR when taking exceptions
When taking an exception print the content of the exception link
register. This is useful especially for synchronous exceptions because
in that case this registers holds the address of the instruction that
generated the exception.

Backports commit b21ab1fc217b4a2b8f2f85d16bdd8510a7817a34 from qemu
2018-02-17 15:23:13 -05:00
Yongbok Kim
97719c5dc0
target-mips: add mips32r6-generic CPU definition
Define a new CPU definition supporting MIPS32 Release 6 ISA and
microMIPS32 Release 6 ISA.

Backports commit 4b3bcd016d83cc75f6a495c1db54b6c77f037adc from qemu
2018-02-17 15:23:13 -05:00
Yongbok Kim
76ab1f17fb
target-mips: microMIPS32 R6 POOL16{A, C} instructions
microMIPS32 Release 6 POOL16A/ POOL16C instructions

Backports commit ed7ce6c0f9d4370826557ce33d652beb88ccb3e6 from qemu
2018-02-17 15:23:13 -05:00
Yongbok Kim
6e6ca4dbd4
target-mips: microMIPS32 R6 Major instructions
Add new microMIPS32 Release 6 Major opcode instructions

Backports commit ab39ee452d74855adec91056812b8e1e5166302c from qemu
2018-02-17 15:23:13 -05:00
Yongbok Kim
c2550bc28a
target-mips: microMIPS32 R6 POOL32{I, C} instructions
Add new microMIPS32 Release 6 POOL32I/POOL32C type instructions

Backports commit 3b4a5489447e7ed17cc504572cf729833853e7ab from qemu
2018-02-17 15:23:12 -05:00
Yongbok Kim
fe7e49dc20
target-mips: microMIPS32 R6 POOL32F instructions
Add new microMIPS32 Release 6 POOL32F instructions

Backports commit 2a24a7badeb6ad3ba72e7984f299623035d564d6 from qemu
2018-02-17 15:23:12 -05:00
Yongbok Kim
f816d6c637
target-mips: microMIPS32 R6 POOL32A{XF} instructions
Add new microMIPS32 Release 6 pool32a/pool32axf instructions.

Backports commit e03320958305a68f2bc6a32c87d7ed48303438f9 from qemu
2018-02-17 15:23:12 -05:00
Yongbok Kim
697b234864
target-mips: microMIPS32 R6 branches and jumps
Add new microMIPS32 Release 6 branch and jump instructions.

Backports commit 65935f070aa710cf340e96ae7ee36d2c1d5c8d15 from qemu
2018-02-17 15:23:12 -05:00
Yongbok Kim
de26dc6854
target-mips: add microMIPS32 R6 opcode enum
Add microMIPS32 Release 6 opcode enum.
Remove RI checking for pre-R6 reserved opcode.

Backports commit 3a1f426828cd8ffeec1a4fa8ca6ca3ed4f800edb from qemu
2018-02-17 15:23:12 -05:00
Yongbok Kim
5cca75ca10
target-mips: signal RI for removed instructions in microMIPS R6
Signal a Reserved Instruction exception for removed instruction encoding
in microMIPS Release 6.

Backports commit 9e8f441a7e094c0dc33a1c8f521d9e5bcfc1b4da from qemu
2018-02-17 15:23:11 -05:00
Yongbok Kim
acede6f50c
target-mips: raise RI exceptions when FIR.PS = 0
64-bit paired-single (PS) floating point data type is optional in the
pre-Release 6.
It has to raise RI exception when PS type is not implemented. (FIR.PS = 0)
(The PS data type is removed in the Release 6.)
Loongson-2E and Loongson-2F don't have any implementation field in
FCSR0(FIR) but do support PS data format, therefore for these cores RI will
not be signalled regardless of PS bit.

Backports commit e29c962804c4dd3fabd44e703aa87eec555ed910 from qemu
2018-02-17 15:23:11 -05:00
Yongbok Kim
90848d778a
target-mips: rearrange gen_compute_compact_branch
The function will be also used for microMIPS Release 6.

Backports commit 6893f07466b045c5faf314ab9e57ef3b4a6f9e49 from qemu
2018-02-17 15:23:11 -05:00
Yongbok Kim
6e32aa7c3c
target-mips: refactor {D}LSA, {D}ALIGN, {D}BITSWAP
Refactor those instructions in order to reuse them for microMIPS32
Release 6.
Rearrange gen_move_low32().

Backports commit 1f1b4c008e250f870719ed38fbd0bcc14322fc01 from qemu
2018-02-17 15:23:11 -05:00
Yongbok Kim
14abf22311
target-mips: remove an unused argument
Remove an unused argument from decode_micromips32_opc()

Backports commit f60eeb0c5ddd8ceb8ca6b3ba032159027afab67a from qemu
2018-02-17 15:23:11 -05:00
Yongbok Kim
9750bc546f
target-mips: add microMIPS TLBINV, TLBINVF
Add microMIPS TLBINV, TLBINVF

Backports commit e60ec06357470db5a0f25901ca19b6237e6da927 from qemu
2018-02-17 15:23:10 -05:00
Yongbok Kim
af0e6e9be3
target-mips: fix {RD, WR}PGPR in microMIPS
rt, rs were swapped

Backports commit 1bf5902de03732d4067c4e90171a1741d6542c45 from qemu
2018-02-17 15:23:10 -05:00
Leon Alrae
80341ab1d8
target-mips: remove identical code in different branch
Backports commit ff334767728011218c62f7476232d260cb5b28e6 from qemu
2018-02-17 15:23:10 -05:00
Markus Armbruster
b5841191bc
qerror: Move #include out of qerror.h 2018-02-17 15:23:10 -05:00
Markus Armbruster
15553fc60d
qerror: Finally unused, clean up
Remove it except for two things in qerror.h:

* Two #include to be cleaned up separately to avoid cluttering this
patch.

* The QERR_ macros. Mark as obsolete.

Backports commit 4629ed1e98961bbe678db68ef5f4342ff174a6c3 from qemu
2018-02-17 15:23:10 -05:00