unicorn/qemu
Peter Maydell 175b632c91
target/arm: Report GICv3 sysregs present in ID registers if needed
The CPU ID registers ID_AA64PFR0_EL1, ID_PFR1_EL1 and ID_PFR1
have a field for reporting presence of GICv3 system registers.
We need to report this field correctly in order for Xen to
work as a guest inside QEMU emulation. We mustn't incorrectly
claim the sysregs exist when they don't, though, or Linux will
crash.

Unfortunately the way we've designed the GICv3 emulation in QEMU
puts the system registers as part of the GICv3 device, which
may be created after the CPU proper has been realized. This
means that we don't know at the point when we define the ID
registers what the correct value is. Handle this by switching
them to calling a function at runtime to read the value, where
we can fill in the GIC field appropriately.

Backports commit 96a8b92ed8f02d5e86ad380d3299d9f41f99b072 from qemu
2018-03-05 13:48:28 -05:00
..
accel tcg: Merge opcode arguments into TCGOp 2018-03-05 04:45:20 -05:00
crypto
default-configs
docs
fpu
hw mips: replace cpu_mips_init() with cpu_generic_init() 2018-03-05 00:49:10 -05:00
include compiler: Add defines for abstracting thread-local storage 2018-03-05 13:48:27 -05:00
qapi
qobject
qom qom: introduce type_register_static_array() 2018-03-05 03:49:50 -05:00
scripts
target target/arm: Report GICv3 sysregs present in ID registers if needed 2018-03-05 13:48:28 -05:00
tcg tcg/s390x: Use constant pool for prologue 2018-03-05 11:28:39 -05:00
util bitmap: provide to_le/from_le helpers 2018-03-05 01:11:13 -05:00
aarch64.h target/arm: Implement BLXNS 2018-03-05 03:31:59 -05:00
aarch64eb.h target/arm: Implement BLXNS 2018-03-05 03:31:59 -05:00
accel.c
arm.h target/arm: Implement BLXNS 2018-03-05 03:31:59 -05:00
armeb.h target/arm: Implement BLXNS 2018-03-05 03:31:59 -05:00
atomic_template.h tcg: Record code_gen_buffer address for user-only memory helpers 2018-03-05 13:48:27 -05:00
CODING_STYLE
configure build: disable -Wmissing-braces on older compilers 2018-03-05 11:29:54 -05:00
COPYING
COPYING.LIB
cpu-exec-common.c
cpu-exec.c exec-all: extract tb->tc_* into a separate struct tc_tb 2018-03-05 02:57:22 -05:00
cpus.c
cputlb.c tcg: Record code_gen_buffer address for user-only memory helpers 2018-03-05 13:48:28 -05:00
exec.c qom: Introduce CPUClass.tcg_initialize 2018-03-05 09:49:26 -05:00
gen_all_header.sh
glib_compat.c
HACKING
header_gen.py qom: Introduce CPUClass.tcg_initialize 2018-03-05 09:49:26 -05:00
ioport.c
LICENSE
m68k.h target/arm: Implement BLXNS 2018-03-05 03:31:59 -05:00
Makefile
Makefile.objs
Makefile.target
memory_ldst.inc.c
memory_mapping.c
memory.c memory: avoid a name clash with access macro 2018-03-05 01:13:01 -05:00
mips64.h target/arm: Implement BLXNS 2018-03-05 03:31:59 -05:00
mips64el.h target/arm: Implement BLXNS 2018-03-05 03:31:59 -05:00
mips.h target/arm: Implement BLXNS 2018-03-05 03:31:59 -05:00
mipsel.h target/arm: Implement BLXNS 2018-03-05 03:31:59 -05:00
powerpc.h target/arm: Implement BLXNS 2018-03-05 03:31:59 -05:00
qapi-schema.json
qemu-timer.c
rules.mak
softmmu_template.h
sparc64.h qom: Introduce CPUClass.tcg_initialize 2018-03-05 09:49:26 -05:00
sparc.h qom: Introduce CPUClass.tcg_initialize 2018-03-05 09:49:26 -05:00
tcg-runtime.c exec-all: extract tb->tc_* into a separate struct tc_tb 2018-03-05 02:57:22 -05:00
translate-all.c tcg: Merge opcode arguments into TCGOp 2018-03-05 04:45:20 -05:00
translate-all.h
translate-common.c
unicorn_common.h
VERSION
vl.c
vl.h import 2015-08-21 15:04:50 +08:00
x86_64.h target/arm: Implement BLXNS 2018-03-05 03:31:59 -05:00