unicorn/qemu/target
Peter Maydell 175b632c91
target/arm: Report GICv3 sysregs present in ID registers if needed
The CPU ID registers ID_AA64PFR0_EL1, ID_PFR1_EL1 and ID_PFR1
have a field for reporting presence of GICv3 system registers.
We need to report this field correctly in order for Xen to
work as a guest inside QEMU emulation. We mustn't incorrectly
claim the sysregs exist when they don't, though, or Linux will
crash.

Unfortunately the way we've designed the GICv3 emulation in QEMU
puts the system registers as part of the GICv3 device, which
may be created after the CPU proper has been realized. This
means that we don't know at the point when we define the ID
registers what the correct value is. Handle this by switching
them to calling a function at runtime to read the value, where
we can fill in the GIC field appropriately.

Backports commit 96a8b92ed8f02d5e86ad380d3299d9f41f99b072 from qemu
2018-03-05 13:48:28 -05:00
..
arm target/arm: Report GICv3 sysregs present in ID registers if needed 2018-03-05 13:48:28 -05:00
i386 target-i386: adds PV_TLB_FLUSH CPUID feature bit 2018-03-05 13:48:28 -05:00
m68k qom: Introduce CPUClass.tcg_initialize 2018-03-05 09:49:26 -05:00
mips qom: Introduce CPUClass.tcg_initialize 2018-03-05 09:49:26 -05:00
sparc qom: Introduce CPUClass.tcg_initialize 2018-03-05 09:49:26 -05:00