unicorn/qemu
Peter Maydell 3df93e463d target/arm: Don't use a TLB for ARMMMUIdx_Stage2
We define ARMMMUIdx_Stage2 as being an MMU index which uses a QEMU
TLB. However we never actually use the TLB -- all stage 2 lookups
are done by direct calls to get_phys_addr_lpae() followed by a
physical address load via address_space_ld*().

Remove Stage2 from the list of ARM MMU indexes which correspond to
real core MMU indexes, and instead put it in the set of "NOTLB" ARM
MMU indexes.

This allows us to drop NB_MMU_MODES to 11. It also means we can
safely add support for the ARMv8.3-TTS2UXN extension, which adds
permission bits to the stage 2 descriptors which define execute
permission separatel for EL0 and EL1; supporting that while keeping
Stage2 in a QEMU TLB would require us to use separate TLBs for
"Stage2 for an EL0 access" and "Stage2 for an EL1 access", which is a
lot of extra complication given we aren't even using the QEMU TLB.

In the process of updating the comment on our MMU index use,
fix a couple of other minor errors:
* NS EL2 EL2&0 was missing from the list in the comment
* some text hadn't been updated from when we bumped NB_MMU_MODES
above 8

Backports commit bf05340cb655637451162c02dadcd6581a05c02c from qemu
2020-05-07 08:40:06 -04:00
..
accel tcg: Remove softmmu code_gen_buffer fixed address 2020-04-30 07:03:06 -04:00
crypto
default-configs
docs
fpu softfloat: Fix BAD_SHIFT from normalizeFloatx80Subnormal 2020-04-30 07:22:57 -04:00
hw
include osdep.h: Drop no-longer-needed Coverity workarounds 2020-04-30 07:27:24 -04:00
qapi
qobject
qom
scripts decodetree: Use Python3 floor division operator 2020-04-30 07:16:30 -04:00
target target/arm: Don't use a TLB for ARMMMUIdx_Stage2 2020-05-07 08:40:06 -04:00
tcg tcg/mips: mips sync* encode error 2020-04-30 07:24:57 -04:00
util
aarch64.h target/arm: Make cpu_register() available for other files 2020-04-30 21:38:42 -04:00
aarch64eb.h target/arm: Make cpu_register() available for other files 2020-04-30 21:38:42 -04:00
accel.c
arm.h target/arm: Make cpu_register() available for other files 2020-04-30 21:38:42 -04:00
armeb.h target/arm: Make cpu_register() available for other files 2020-04-30 21:38:42 -04:00
CODING_STYLE.rst
configure configure: Support -static-pie if requested 2020-04-30 07:09:34 -04:00
COPYING
COPYING.LIB
cpus.c
exec.c
gen_all_header.sh
glib_compat.c target/arm: Add VHE system register redirection and aliasing 2020-03-21 15:57:03 -04:00
header_gen.py target/arm: Make cpu_register() available for other files 2020-04-30 21:38:42 -04:00
ioport.c
LICENSE
m68k.h target/arm: Make cpu_register() available for other files 2020-04-30 21:38:42 -04:00
Makefile
Makefile.objs
Makefile.target
memory_ldst.inc.c
memory_mapping.c
memory.c
mips64.h target/arm: Make cpu_register() available for other files 2020-04-30 21:38:42 -04:00
mips64el.h target/arm: Make cpu_register() available for other files 2020-04-30 21:38:42 -04:00
mips.h target/arm: Make cpu_register() available for other files 2020-04-30 21:38:42 -04:00
mipsel.h target/arm: Make cpu_register() available for other files 2020-04-30 21:38:42 -04:00
powerpc.h target/arm: Make cpu_register() available for other files 2020-04-30 21:38:42 -04:00
qemu-timer.c
riscv32.h target/arm: Make cpu_register() available for other files 2020-04-30 21:38:42 -04:00
riscv64.h target/arm: Make cpu_register() available for other files 2020-04-30 21:38:42 -04:00
rules.mak
sparc64.h target/arm: Make cpu_register() available for other files 2020-04-30 21:38:42 -04:00
sparc.h target/arm: Make cpu_register() available for other files 2020-04-30 21:38:42 -04:00
unicorn_common.h
VERSION Open 5.1 development tree 2020-04-30 07:30:38 -04:00
vl.c
vl.h
x86_64.h target/arm: Make cpu_register() available for other files 2020-04-30 21:38:42 -04:00