Peter Maydell 4ea6fdc986 target-arm: A64: Avoid left shifting negative integers in disas_pc_rel_addr ... Shifting a negative integer left is undefined behaviour in C. Avoid it by assembling and shifting the offset fields as unsigned values and then sign extending as the final action. Backports commit 037e1d009e2fcb80784d37f0e12aa999787d46d4 from qemu		2018-02-12 15:04:03 -05:00
..
default-configs
docs	cleanup qemu docs	2017-01-18 15:23:40 +08:00
fpu	softfloat: expand out STATUS macro	2018-02-12 13:43:13 -05:00
hw
include	softfloat: expand out STATUS macro	2018-02-12 13:43:13 -05:00
qapi
qobject
qom
scripts
target-arm	target-arm: A64: Avoid left shifting negative integers in disas_pc_rel_addr	2018-02-12 15:04:03 -05:00
target-i386	target-i386: make xmm_regs 512-bit wide	2018-02-12 12:38:43 -05:00
target-m68k	target-*: Increment num_insns immediately after tcg_gen_insn_start	2018-02-11 12:46:30 -05:00
target-mips	softfloat: expand out STATUS_VAR	2018-02-12 13:36:42 -05:00
target-sparc	target-*: Increment num_insns immediately after tcg_gen_insn_start	2018-02-11 12:46:30 -05:00
tcg	tcg: Allow extra data to be attached to insn_start	2018-02-11 13:03:51 -05:00
util
aarch64.h	target-arm: Add 32/64-bit register sync	2018-02-12 14:57:20 -05:00
aarch64eb.h	target-arm: Add 32/64-bit register sync	2018-02-12 14:57:20 -05:00
accel.c
arm.h	target-arm: Add 32/64-bit register sync	2018-02-12 14:57:20 -05:00
armeb.h	target-arm: Add 32/64-bit register sync	2018-02-12 14:57:20 -05:00
CODING_STYLE
configure	tcg: Drop ia64 host support	2018-02-04 18:33:02 -05:00
COPYING
COPYING.LIB
cpu-exec.c
cpus.c
cputlb.c
exec.c
gen_all_header.sh
glib_compat.c
HACKING
header_gen.py	target-arm: Add 32/64-bit register sync	2018-02-12 14:57:20 -05:00
ioport.c	This code should now build the x86_x64-softmmu part 2.	2017-01-19 22:50:28 +11:00
LICENSE
m68k.h	target-arm: Add 32/64-bit register sync	2018-02-12 14:57:20 -05:00
Makefile
Makefile.objs
Makefile.target	tcg: Move some opcode generation functions out of line	2018-02-09 08:10:00 -05:00
memory_mapping.c
memory.c	merge msvc with master	2017-02-24 10:39:36 +08:00
mips64.h	target-arm: Add 32/64-bit register sync	2018-02-12 14:57:20 -05:00
mips64el.h	target-arm: Add 32/64-bit register sync	2018-02-12 14:57:20 -05:00
mips.h	target-arm: Add 32/64-bit register sync	2018-02-12 14:57:20 -05:00
mipsel.h	target-arm: Add 32/64-bit register sync	2018-02-12 14:57:20 -05:00
powerpc.h	target-arm: Add 32/64-bit register sync	2018-02-12 14:57:20 -05:00
qapi-schema.json
qemu-log.c
qemu-timer.c
rules.mak
softmmu_template.h	tcg: Add MO_ALIGN, MO_UNALN	2018-02-10 20:18:53 -05:00
sparc64.h	target-arm: Add 32/64-bit register sync	2018-02-12 14:57:20 -05:00
sparc.h	target-arm: Add 32/64-bit register sync	2018-02-12 14:57:20 -05:00
tcg-runtime.c
translate-all.c	target-mips: Correct MIPS16/microMIPS branch size calculation	2018-02-11 16:09:33 -05:00
translate-all.h
unicorn_common.h
VERSION
vl.c
vl.h
x86_64.h	target-arm: Add 32/64-bit register sync	2018-02-12 14:57:20 -05:00