unicorn/qemu/target-i386
Lioncash 6b19f43925
tcg: Make cpu_tmp1 and cpu_tmp4 a TCGv
Commit 5d4e1a1081d3f1ec2908ff0eaebe312389971ab4 allows
making the type concrete.
2018-02-21 00:07:23 -05:00
..
arch_memory_mapping.c x86: Clean up includes 2018-02-19 01:00:09 -05:00
bpt_helper.c x86: Clean up includes 2018-02-19 01:00:09 -05:00
cc_helper_template.h
cc_helper.c target-i386: Perform set/reset_inhibit_irq inline 2018-02-20 13:34:47 -05:00
cpu-qom.h
cpu.c target-i386: fix confusion in xcr0 bit position vs. mask 2018-02-20 21:00:41 -05:00
cpu.h target-i386: fix confusion in xcr0 bit position vs. mask 2018-02-20 21:00:41 -05:00
excp_helper.c x86: Clean up includes 2018-02-19 01:00:09 -05:00
fpu_helper.c target-i386: fix confusion in xcr0 bit position vs. mask 2018-02-20 21:00:41 -05:00
helper.c target-i386: Enable control registers for MPX 2018-02-20 13:27:46 -05:00
helper.h target-i386: Implement FSGSBASE 2018-02-20 14:45:58 -05:00
int_helper.c target-i386: Implement FSGSBASE 2018-02-20 14:45:58 -05:00
Makefile.objs target-i386: Enable control registers for MPX 2018-02-20 13:27:46 -05:00
mem_helper.c target-i386: Update BNDSTATUS for exceptions raised by BOUND 2018-02-20 14:24:07 -05:00
misc_helper.c target-i386: Enable control registers for MPX 2018-02-20 13:27:46 -05:00
mpx_helper.c target-i386: fix confusion in xcr0 bit position vs. mask 2018-02-20 21:00:41 -05:00
ops_sse_header.h target-i386: Rename struct XMMReg to ZMMReg 2018-02-18 23:46:30 -05:00
ops_sse.h target-i386: Rename XMM_[BWLSDQ] helpers to ZMM_* 2018-02-18 23:53:16 -05:00
seg_helper.c target-i386: Rewrite gen_enter inline 2018-02-20 10:13:43 -05:00
shift_helper_template.h
smm_helper.c target-i386: Enable control registers for MPX 2018-02-20 13:27:46 -05:00
svm_helper.c x86: Clean up includes 2018-02-19 01:00:09 -05:00
svm.h
TODO
topology.h
translate.c tcg: Make cpu_tmp1 and cpu_tmp4 a TCGv 2018-02-21 00:07:23 -05:00
unicorn.c tcg: Make cpu_tmp1 and cpu_tmp4 a TCGv 2018-02-21 00:07:23 -05:00
unicorn.h