Peter Crosthwaite 63e5f57bb2 target-arm: Add support for Cortex-R5 ... Introduce a CPU model for the Cortex R5 processor. ARMv7 with MPU, and both thumb and ARM div instructions. Also implement dummy ATCM and BTCM. These CPs are defined for R5 but don't have a lot of meaning in QEMU yet. Raz them so the guest can proceed if they are read. The TCM registers will return a size of 0, indicating no TCM. Backports commit d6a6b13ea1dfeb25c43a648e94cfe4395906f1da from qemu		2018-02-17 15:23:08 -05:00
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arm_ldst.h
cpu64.c	target-arm: Fix REVIDR reset value	2018-02-13 14:24:08 -05:00
cpu-qom.h	target-arm/helper.c: define MPUIR register	2018-02-17 15:22:43 -05:00
cpu.c	target-arm: Add support for Cortex-R5	2018-02-17 15:23:08 -05:00
cpu.h	target-arm: Implement PMSAv7 MPU	2018-02-17 15:23:08 -05:00
crypto_helper.c	target-arm: crypto: fix BE host support	2018-02-12 10:40:52 -05:00
helper-a64.c	target-arm: Update interrupt handling to use target EL	2018-02-12 22:42:37 -05:00
helper-a64.h
helper.c	target-arm: Implement PMSAv7 MPU	2018-02-17 15:23:08 -05:00
helper.h	target-arm: Add exception target el infrastructure	2018-02-12 22:17:02 -05:00
internals.h	arm: Refactor get_phys_addr FSR return mechanism	2018-02-17 15:22:42 -05:00
iwmmxt_helper.c
kvm-consts.h
Makefile.objs
neon_helper.c
op_addsub.h
op_helper.c	arm: Refactor get_phys_addr FSR return mechanism	2018-02-17 15:22:42 -05:00
psci.c
translate-a64.c	target-arm: Don't halt on WFI unless we don't have any work	2018-02-12 23:10:45 -05:00
translate.c	target-arm: Correct "preferred return address" for cpreg access exceptions	2018-02-17 15:22:42 -05:00
translate.h	target-arm: Extend FP checks to use an EL	2018-02-12 23:04:19 -05:00
unicorn_aarch64.c	target-arm: rename c1_coproc to cpacr_el1	2018-02-12 20:46:00 -05:00
unicorn_arm.c	target-arm: Add registers for PMSAv7	2018-02-17 15:22:43 -05:00
unicorn.h