unicorn/qemu/target/mips
James Hogan 4cc63bac09
target/mips: Fix RDHWR CC with icount
RDHWR CC reads the CPU timer like MFC0 CP0_Count, so with icount enabled
it must set can_do_io while it calls the helper to avoid the "Bad icount
read" error. It should also break out of the translation loop to ensure
that timer interrupts are immediately handled.

Backports commit d673a68db6963e86536b125af464bb6ed03eba33 from qemu
2018-03-04 01:35:25 -05:00
..
cpu-qom.h
cpu.c
cpu.h target/mips: Add segmentation control registers 2018-03-04 01:00:42 -05:00
dsp_helper.c
helper.c mips: Improve segment defs for KVM T&E guests 2018-03-04 01:26:42 -05:00
helper.h target/mips: Add segmentation control registers 2018-03-04 01:00:42 -05:00
lmi_helper.c
Makefile.objs
mips-defs.h
msa_helper.c
op_helper.c target-mips: apply CP0.PageMask before writing into TLB entry 2018-03-04 01:27:51 -05:00
TODO
translate_init.c target/mips: Enable CP0_EBase.WG on MIPS64 CPUs 2018-03-04 01:09:47 -05:00
translate.c target/mips: Fix RDHWR CC with icount 2018-03-04 01:35:25 -05:00
unicorn.c
unicorn.h