unicorn/qemu/target
Peter Maydell a897ee919b
target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode
For v7M, writes to the CONTROL register are only permitted for
privileged code. However even if the code is privileged, the
write must not affect the SPSEL bit in the CONTROL register
if the CPU is in Thread mode (as documented in the pseudocode
for the MSR instruction). Implement this, instead of permitting
SPSEL to be written in all cases.

This was causing mbed applications not to run, because the
RTX RTOS they use relies on this behaviour.

Backports commit 792dac309c8660306557ba058b8b5a6a75ab3c1f from qemu
2018-03-04 13:04:20 -05:00
..
arm target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode 2018-03-04 13:04:20 -05:00
i386 target-i386/cpu: Add new EPYC CPU model 2018-03-04 12:22:27 -05:00
m68k tcg: Pass generic CPUState to gen_intermediate_code() 2018-03-03 23:34:18 -05:00
mips target/mips: Fix RDHWR CC with icount 2018-03-04 01:35:25 -05:00
sparc tcg: Pass generic CPUState to gen_intermediate_code() 2018-03-03 23:34:18 -05:00