Richard Henderson a968769d26 target/riscv: Use pattern groups in insn16.decode ... This eliminates about half of the complicated decode bits within insn_trans/trans_rvc.inc.c. Backports commit c2cfb97c01a3636867c1a4a24f8a99fd8c6bed28 from qemu		2019-05-28 18:55:28 -04:00
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trans_privileged.inc.c	RISC-V: fix single stepping over ret and other branching instructions	2019-05-28 18:35:07 -04:00
trans_rva.inc.c	target/riscv: Convert RV64A insns to decodetree	2019-03-18 16:27:53 -04:00
trans_rvc.inc.c	target/riscv: Use pattern groups in insn16.decode	2019-05-28 18:55:28 -04:00
trans_rvd.inc.c	target/riscv: Convert RV64D insns to decodetree	2019-03-18 16:57:16 -04:00
trans_rvf.inc.c	target/riscv: Convert RV64F insns to decodetree	2019-03-18 16:43:17 -04:00
trans_rvi.inc.c	target/riscv: Use pattern groups in insn16.decode	2019-05-28 18:55:28 -04:00
trans_rvm.inc.c	target/riscv: Zero extend the inputs of divuw and remuw	2019-03-26 20:38:17 -04:00