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https://github.com/yuzu-emu/unicorn.git
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a968769d26
This eliminates about half of the complicated decode bits within insn_trans/trans_rvc.inc.c. Backports commit c2cfb97c01a3636867c1a4a24f8a99fd8c6bed28 from qemu
116 lines
3.1 KiB
C
116 lines
3.1 KiB
C
/*
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* RISC-V translation routines for the RVC Compressed Instruction Set.
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
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* Bastian Koppelmann, kbastian@mail.uni-paderborn.de
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
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{
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#ifdef TARGET_RISCV32
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/* C.FLW ( RV32FC-only ) */
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REQUIRE_FPU;
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REQUIRE_EXT(ctx, RVF);
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arg_i arg;
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decode_insn16_extract_cl_w(ctx, &arg, ctx->opcode);
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return trans_flw(ctx, &arg);
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#else
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/* C.LD ( RV64C/RV128C-only ) */
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arg_i arg;
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decode_insn16_extract_cl_d(ctx, &arg, ctx->opcode);
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return trans_ld(ctx, &arg);
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#endif
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}
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static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
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{
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#ifdef TARGET_RISCV32
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/* C.FSW ( RV32FC-only ) */
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REQUIRE_FPU;
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REQUIRE_EXT(ctx, RVF);
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arg_s arg;
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decode_insn16_extract_cs_w(ctx, &arg, ctx->opcode);
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return trans_fsw(ctx, &arg);
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#else
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/* C.SD ( RV64C/RV128C-only ) */
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arg_s arg;
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decode_insn16_extract_cs_d(ctx, &arg, ctx->opcode);
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return trans_sd(ctx, &arg);
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#endif
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}
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static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
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{
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#ifdef TARGET_RISCV32
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/* C.JAL */
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arg_j tmp;
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decode_insn16_extract_cj(ctx, &tmp, ctx->opcode);
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arg_jal arg = { .rd = 1, .imm = tmp.imm };
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return trans_jal(ctx, &arg);
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#else
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/* C.ADDIW */
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arg_addiw arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
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return trans_addiw(ctx, &arg);
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#endif
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}
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static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
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{
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#ifdef TARGET_RISCV64
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return trans_subw(ctx, a);
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#else
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return false;
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#endif
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}
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static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
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{
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#ifdef TARGET_RISCV64
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return trans_addw(ctx, a);
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#else
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return false;
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#endif
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}
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static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
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{
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#ifdef TARGET_RISCV32
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/* C.FLWSP */
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arg_flw arg_flw = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_flwsp };
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return trans_flw(ctx, &arg_flw);
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#else
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/* C.LDSP */
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arg_ld arg_ld = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_ldsp };
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return trans_ld(ctx, &arg_ld);
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#endif
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return false;
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}
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static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
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{
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#ifdef TARGET_RISCV32
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/* C.FSWSP */
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arg_fsw a_fsw = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_fswsp };
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return trans_fsw(ctx, &a_fsw);
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#else
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/* C.SDSP */
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arg_sd a_sd = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_sdsp };
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return trans_sd(ctx, &a_sd);
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#endif
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}
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