Sergey Fedorov b42bfc59f1 target-arm: Update condexec before CP access check in AA32 translation ... Coprocessor access instructions are allowed inside IT block. gen_helper_access_check_cp_reg() can raise an exceptions thus condexec bits should be updated before. Backports commit 43bfa4a100687af8d293fef0a197839b51400fca from qemu		2018-02-17 18:33:58 -05:00
..
arm_ldst.h
cpu64.c	target-arm: Fix REVIDR reset value	2018-02-13 14:24:08 -05:00
cpu-qom.h	target-arm: Refactor CPU affinity handling	2018-02-17 15:23:34 -05:00
cpu.c	target-arm: Refactor CPU affinity handling	2018-02-17 15:23:34 -05:00
cpu.h	target-arm: Add HPFAR_EL2	2018-02-17 15:24:07 -05:00
crypto_helper.c	crypto: move built-in AES implementation into crypto/	2018-02-17 15:23:17 -05:00
helper-a64.c	target-arm: Log the target EL when taking exceptions	2018-02-17 15:23:36 -05:00
helper-a64.h
helper.c	target-arm: Add and use symbolic names for register banks	2018-02-17 18:14:14 -05:00
helper.h	target-arm: Fix CPU breakpoint handling	2018-02-17 15:24:02 -05:00
internals.h	target-arm: Add and use symbolic names for register banks	2018-02-17 18:14:14 -05:00
iwmmxt_helper.c
kvm-consts.h
Makefile.objs	delete sparc32_dma.h & arm-semi.c	2017-01-19 15:10:41 +08:00
neon_helper.c	Arm support ported. (#736)	2017-01-23 23:30:57 +08:00
op_addsub.h
op_helper.c	target-arm: Add and use symbolic names for register banks	2018-02-17 18:14:14 -05:00
psci.c
translate-a64.c	target-arm: Report S/NS status in the CPU debug logs	2018-02-17 15:24:14 -05:00
translate.c	target-arm: Update condexec before CP access check in AA32 translation	2018-02-17 18:33:58 -05:00
translate.h	tcg: Remove gen_intermediate_code_pc	2018-02-17 15:23:59 -05:00
unicorn_aarch64.c	target-arm: rename c1_coproc to cpacr_el1	2018-02-12 20:46:00 -05:00
unicorn_arm.c	target-arm: Add registers for PMSAv7	2018-02-17 15:22:43 -05:00
unicorn.h	arm64eb: add support for ARM64 big endian.	2017-04-24 23:30:01 +08:00