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b6f752970b
This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
14 lines
360 B
C
14 lines
360 B
C
#define xRA 1 /* return address (aka link register) */
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#define xSP 2 /* stack pointer */
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#define xGP 3 /* global pointer */
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#define xTP 4 /* thread pointer */
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#define xA0 10 /* gpr[10-17] are syscall arguments */
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#define xA1 11
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#define xA2 12
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#define xA3 13
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#define xA4 14
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#define xA5 15
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#define xA6 16
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#define xA7 17 /* syscall number goes here */
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