unicorn/qemu/target/riscv
Lioncash b6f752970b
target/riscv: Initial introduction of the RISC-V target
This ports over the RISC-V architecture from Qemu. This is currently a
very barebones transition. No code hooking or any fancy stuff.
Currently, you can feed it instructions and query the CPU state itself.

This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit
is desirable through Unicorn's interface as well.

Extremely basic examples of executing a single instruction have been
added to the samples directory to help demonstrate how to use the basic
functionality.
2019-03-08 21:46:10 -05:00
..
cpu_bits.h target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
cpu_helper.c target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
cpu_user.h target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
cpu.c target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
cpu.h target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
csr.c target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
fpu_helper.c target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
helper.h target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
instmap.h target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
Makefile.objs target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
op_helper.c target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
pmp.c target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
pmp.h target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
translate.c target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
unicorn.c target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
unicorn.h target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00