Richard Henderson 68ce00ac2f target/riscv: Split gen_arith_imm into functional and temp ... The tcg_gen_fooi_tl functions have some immediate constant folding built in, which match up with some of the riscv asm builtin macros, like mv and not. Backports commit 598aa1160c3d17ab9271daf1f69d093ebada3f25 from qemu		2019-05-28 19:07:53 -04:00
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trans_privileged.inc.c	RISC-V: fix single stepping over ret and other branching instructions	2019-05-28 18:35:07 -04:00
trans_rva.inc.c	target/riscv: Convert RV64A insns to decodetree	2019-03-18 16:27:53 -04:00
trans_rvd.inc.c	target/riscv: Convert RV64D insns to decodetree	2019-03-18 16:57:16 -04:00
trans_rvf.inc.c	target/riscv: Convert RV64F insns to decodetree	2019-03-18 16:43:17 -04:00
trans_rvi.inc.c	target/riscv: Split gen_arith_imm into functional and temp	2019-05-28 19:07:53 -04:00
trans_rvm.inc.c	target/riscv: Zero extend the inputs of divuw and remuw	2019-03-26 20:38:17 -04:00