Michael Clark d3dbcb6dfc RISC-V: Add support for vectored interrupts ... If vectored interrupts are enabled (bits[1:0] of mtvec/stvec == 1) then use the following logic for trap entry address calculation: pc = mtvec + cause * 4 In addition to adding support for vectored interrupts this patch simplifies the interrupt delivery logic by making sync/async cause decoding and encoding steps distinct. The cause code and the sign bit indicating sync/async is split at the beginning of the function and fixed cause is renamed to cause. The MSB setting for async traps is delayed until setting mcause/scause to allow redundant variables to be eliminated. Some variables are renamed for conciseness and moved so that decls are at the start of the block. Backports commit acbbb94e5730c9808830938e869d243014e2923a from qemu		2019-03-19 23:58:31 -04:00
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insn_trans	target/riscv: Fix manually parsed 16 bit insn	2019-03-19 05:44:58 -04:00
cpu_bits.h	RISC-V: Fixes to CSR_* register macros.	2019-03-19 23:39:49 -04:00
cpu_helper.c	RISC-V: Add support for vectored interrupts	2019-03-19 23:58:31 -04:00
cpu_user.h	RISC-V: linux-user support for RVE ABI	2019-03-19 23:58:31 -04:00
cpu.c
cpu.h	RISC-V: linux-user support for RVE ABI	2019-03-19 23:58:31 -04:00
csr.c	RISC-V: Add support for vectored interrupts	2019-03-19 23:58:31 -04:00
fpu_helper.c
helper.h
insn16.decode	target/riscv: Convert quadrant 2 of RVXC insns to decodetree	2019-03-19 04:53:07 -04:00
insn32-64.decode	target/riscv: Convert RV64D insns to decodetree	2019-03-18 16:57:16 -04:00
insn32.decode	target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists	2019-03-19 05:17:54 -04:00
instmap.h
Makefile.objs	target/riscv: Convert quadrant 0 of RVXC insns to decodetree	2019-03-19 04:45:53 -04:00
op_helper.c
pmp.c	riscv: pmp: Log pmp access errors as guest errors	2019-03-19 23:45:03 -04:00
pmp.h
translate.c	target/riscv: Remove decode_RV32_64G()	2019-03-19 05:37:42 -04:00
unicorn.c
unicorn.h