mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2024-10-21 09:58:18 +02:00
d3dbcb6dfc
If vectored interrupts are enabled (bits[1:0] of mtvec/stvec == 1) then use the following logic for trap entry address calculation: pc = mtvec + cause * 4 In addition to adding support for vectored interrupts this patch simplifies the interrupt delivery logic by making sync/async cause decoding and encoding steps distinct. The cause code and the sign bit indicating sync/async is split at the beginning of the function and fixed cause is renamed to cause. The MSB setting for async traps is delayed until setting mcause/scause to allow redundant variables to be eliminated. Some variables are renamed for conciseness and moved so that decls are at the start of the block. Backports commit acbbb94e5730c9808830938e869d243014e2923a from qemu
538 lines
18 KiB
C
538 lines
18 KiB
C
/*
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* RISC-V CPU helpers for qemu.
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017-2018 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "tcg-op.h"
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#define RISCV_DEBUG_INTERRUPT 0
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int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
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{
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#ifdef CONFIG_USER_ONLY
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return 0;
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#else
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return env->priv;
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#endif
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}
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#ifndef CONFIG_USER_ONLY
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static int riscv_cpu_local_irq_pending(CPURISCVState *env)
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{
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target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE);
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target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE);
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target_ulong pending = atomic_read(&env->mip) & env->mie;
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target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M && mstatus_mie);
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target_ulong sie = env->priv < PRV_S || (env->priv == PRV_S && mstatus_sie);
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target_ulong irqs = (pending & ~env->mideleg & -mie) |
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(pending & env->mideleg & -sie);
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if (irqs) {
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return ctz64(irqs); /* since non-zero */
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} else {
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return EXCP_NONE; /* indicates no pending interrupt */
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}
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}
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#endif
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bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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#if !defined(CONFIG_USER_ONLY)
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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RISCVCPU *cpu = RISCV_CPU(cs->uc, cs);
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CPURISCVState *env = &cpu->env;
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int interruptno = riscv_cpu_local_irq_pending(env);
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if (interruptno >= 0) {
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cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno;
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riscv_cpu_do_interrupt(cs);
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return true;
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}
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}
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#endif
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return false;
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}
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#if !defined(CONFIG_USER_ONLY)
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int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
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{
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CPURISCVState *env = &cpu->env;
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if (env->miclaim & interrupts) {
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return -1;
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} else {
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env->miclaim |= interrupts;
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return 0;
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}
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}
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/* iothread_mutex must be held */
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uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
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{
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CPURISCVState *env = &cpu->env;
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uint32_t old, new, cmp = atomic_read(&env->mip);
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do {
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old = cmp;
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new = (old & ~mask) | (value & mask);
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cmp = atomic_cmpxchg(&env->mip, old, new);
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} while (old != cmp);
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if (new) {
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cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
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} else {
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cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
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}
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return old;
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}
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void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
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{
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if (newpriv > PRV_M) {
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g_assert_not_reached();
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}
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if (newpriv == PRV_H) {
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newpriv = PRV_U;
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}
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/* tlb_flush is unnecessary as mode is contained in mmu_idx */
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env->priv = newpriv;
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}
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/* get_physical_address - get the physical address for this virtual address
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*
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* Do a page table walk to obtain the physical address corresponding to a
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* virtual address. Returns 0 if the translation was successful
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*
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* Adapted from Spike's mmu_t::translate and mmu_t::walk
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*
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*/
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static int get_physical_address(CPURISCVState *env, hwaddr *physical,
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int *prot, target_ulong addr,
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int access_type, int mmu_idx)
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{
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/* NOTE: the env->pc value visible here will not be
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* correct, but the value visible to the exception handler
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* (riscv_cpu_do_interrupt) is correct */
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int mode = mmu_idx;
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if (mode == PRV_M && access_type != MMU_INST_FETCH) {
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if (get_field(env->mstatus, MSTATUS_MPRV)) {
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mode = get_field(env->mstatus, MSTATUS_MPP);
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}
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}
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if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) {
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*physical = addr;
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return TRANSLATE_SUCCESS;
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}
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*prot = 0;
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target_ulong base;
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int levels, ptidxbits, ptesize, vm, sum;
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int mxr = get_field(env->mstatus, MSTATUS_MXR);
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if (env->priv_ver >= PRIV_VERSION_1_10_0) {
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base = get_field(env->satp, SATP_PPN) << PGSHIFT;
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sum = get_field(env->mstatus, MSTATUS_SUM);
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vm = get_field(env->satp, SATP_MODE);
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switch (vm) {
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case VM_1_10_SV32:
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levels = 2; ptidxbits = 10; ptesize = 4; break;
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case VM_1_10_SV39:
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levels = 3; ptidxbits = 9; ptesize = 8; break;
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case VM_1_10_SV48:
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levels = 4; ptidxbits = 9; ptesize = 8; break;
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case VM_1_10_SV57:
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levels = 5; ptidxbits = 9; ptesize = 8; break;
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case VM_1_10_MBARE:
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*physical = addr;
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return TRANSLATE_SUCCESS;
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default:
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g_assert_not_reached();
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}
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} else {
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base = env->sptbr << PGSHIFT;
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sum = !get_field(env->mstatus, MSTATUS_PUM);
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vm = get_field(env->mstatus, MSTATUS_VM);
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switch (vm) {
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case VM_1_09_SV32:
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levels = 2; ptidxbits = 10; ptesize = 4; break;
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case VM_1_09_SV39:
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levels = 3; ptidxbits = 9; ptesize = 8; break;
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case VM_1_09_SV48:
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levels = 4; ptidxbits = 9; ptesize = 8; break;
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case VM_1_09_MBARE:
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*physical = addr;
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return TRANSLATE_SUCCESS;
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default:
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g_assert_not_reached();
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}
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}
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CPUState *cs = CPU(riscv_env_get_cpu(env));
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int va_bits = PGSHIFT + levels * ptidxbits;
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target_ulong mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
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target_ulong masked_msbs = (addr >> (va_bits - 1)) & mask;
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if (masked_msbs != 0 && masked_msbs != mask) {
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return TRANSLATE_FAIL;
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}
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int ptshift = (levels - 1) * ptidxbits;
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int i;
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#if !TCG_OVERSIZED_GUEST
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restart:
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#endif
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for (i = 0; i < levels; i++, ptshift -= ptidxbits) {
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target_ulong idx = (addr >> (PGSHIFT + ptshift)) &
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((1 << ptidxbits) - 1);
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/* check that physical address of PTE is legal */
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target_ulong pte_addr = base + idx * ptesize;
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#if defined(TARGET_RISCV32)
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target_ulong pte = ldl_phys(cs->as, pte_addr);
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#elif defined(TARGET_RISCV64)
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target_ulong pte = ldq_phys(cs->as, pte_addr);
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#endif
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target_ulong ppn = pte >> PTE_PPN_SHIFT;
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if (!(pte & PTE_V)) {
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/* Invalid PTE */
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return TRANSLATE_FAIL;
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} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
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/* Inner PTE, continue walking */
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base = ppn << PGSHIFT;
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} else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
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/* Reserved leaf PTE flags: PTE_W */
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return TRANSLATE_FAIL;
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} else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) {
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/* Reserved leaf PTE flags: PTE_W + PTE_X */
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return TRANSLATE_FAIL;
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} else if ((pte & PTE_U) && ((mode != PRV_U) &&
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(!sum || access_type == MMU_INST_FETCH))) {
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/* User PTE flags when not U mode and mstatus.SUM is not set,
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or the access type is an instruction fetch */
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return TRANSLATE_FAIL;
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} else if (!(pte & PTE_U) && (mode != PRV_S)) {
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/* Supervisor PTE flags when not S mode */
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return TRANSLATE_FAIL;
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} else if (ppn & ((1ULL << ptshift) - 1)) {
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/* Misaligned PPN */
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return TRANSLATE_FAIL;
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} else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) ||
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((pte & PTE_X) && mxr))) {
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/* Read access check failed */
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return TRANSLATE_FAIL;
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} else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) {
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/* Write access check failed */
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return TRANSLATE_FAIL;
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} else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) {
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/* Fetch access check failed */
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return TRANSLATE_FAIL;
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} else {
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/* if necessary, set accessed and dirty bits. */
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target_ulong updated_pte = pte | PTE_A |
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(access_type == MMU_DATA_STORE ? PTE_D : 0);
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/* Page table updates need to be atomic with MTTCG enabled */
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if (updated_pte != pte) {
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/*
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* - if accessed or dirty bits need updating, and the PTE is
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* in RAM, then we do so atomically with a compare and swap.
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* - if the PTE is in IO space or ROM, then it can't be updated
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* and we return TRANSLATE_FAIL.
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* - if the PTE changed by the time we went to update it, then
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* it is no longer valid and we must re-walk the page table.
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*/
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MemoryRegion *mr;
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hwaddr l = sizeof(target_ulong), addr1;
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mr = address_space_translate(cs->as, pte_addr,
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&addr1, &l, false);
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if (memory_region_is_ram(mr)) {
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target_ulong *pte_pa =
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qemu_map_ram_ptr(env->uc, mr->ram_block, addr1);
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#if TCG_OVERSIZED_GUEST
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/* MTTCG is not enabled on oversized TCG guests so
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* page table updates do not need to be atomic */
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*pte_pa = pte = updated_pte;
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#else
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target_ulong old_pte =
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atomic_cmpxchg(pte_pa, pte, updated_pte);
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if (old_pte != pte) {
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goto restart;
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} else {
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pte = updated_pte;
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}
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#endif
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} else {
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/* misconfigured PTE in ROM (AD bits are not preset) or
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* PTE is in IO space and can't be updated atomically */
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return TRANSLATE_FAIL;
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}
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}
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/* for superpage mappings, make a fake leaf PTE for the TLB's
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benefit. */
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target_ulong vpn = addr >> PGSHIFT;
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*physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT;
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/* set permissions on the TLB entry */
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if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
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*prot |= PAGE_READ;
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}
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if ((pte & PTE_X)) {
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*prot |= PAGE_EXEC;
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}
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/* add write permission on stores or if the page is already dirty,
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so that we TLB miss on later writes to update the dirty bit */
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if ((pte & PTE_W) &&
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(access_type == MMU_DATA_STORE || (pte & PTE_D))) {
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*prot |= PAGE_WRITE;
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}
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return TRANSLATE_SUCCESS;
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}
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}
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return TRANSLATE_FAIL;
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}
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static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
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MMUAccessType access_type)
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{
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CPUState *cs = CPU(riscv_env_get_cpu(env));
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int page_fault_exceptions =
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(env->priv_ver >= PRIV_VERSION_1_10_0) &&
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get_field(env->satp, SATP_MODE) != VM_1_10_MBARE;
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switch (access_type) {
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case MMU_INST_FETCH:
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cs->exception_index = page_fault_exceptions ?
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RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT;
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break;
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case MMU_DATA_LOAD:
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cs->exception_index = page_fault_exceptions ?
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RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT;
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break;
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case MMU_DATA_STORE:
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cs->exception_index = page_fault_exceptions ?
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RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
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break;
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default:
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g_assert_not_reached();
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}
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env->badaddr = address;
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}
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hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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RISCVCPU *cpu = RISCV_CPU(cs->uc, cs);
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hwaddr phys_addr;
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int prot;
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int mmu_idx = cpu_mmu_index(&cpu->env, false);
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if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx)) {
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return -1;
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}
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return phys_addr;
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}
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void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
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MMUAccessType access_type, int mmu_idx,
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uintptr_t retaddr)
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{
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RISCVCPU *cpu = RISCV_CPU(cs->uc, cs);
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CPURISCVState *env = &cpu->env;
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switch (access_type) {
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case MMU_INST_FETCH:
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cs->exception_index = RISCV_EXCP_INST_ADDR_MIS;
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break;
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case MMU_DATA_LOAD:
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cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS;
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break;
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case MMU_DATA_STORE:
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cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS;
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break;
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default:
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g_assert_not_reached();
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}
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env->badaddr = addr;
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riscv_raise_exception(env, cs->exception_index, retaddr);
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}
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/* called by qemu's softmmu to fill the qemu tlb */
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void tlb_fill(CPUState *cs, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
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{
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int ret;
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ret = riscv_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx);
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if (ret == TRANSLATE_FAIL) {
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RISCVCPU *cpu = RISCV_CPU(cs->uc, cs);
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CPURISCVState *env = &cpu->env;
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riscv_raise_exception(env, cs->exception_index, retaddr);
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}
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}
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#endif
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int riscv_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
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int rw, int mmu_idx)
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{
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RISCVCPU *cpu = RISCV_CPU(cs->uc, cs);
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CPURISCVState *env = &cpu->env;
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#if !defined(CONFIG_USER_ONLY)
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hwaddr pa = 0;
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int prot;
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#endif
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int ret = TRANSLATE_FAIL;
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qemu_log_mask(CPU_LOG_MMU,
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"%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx \
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%d\n", __func__, env->pc, address, rw, mmu_idx);
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#if !defined(CONFIG_USER_ONLY)
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ret = get_physical_address(env, &pa, &prot, address, rw, mmu_idx);
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qemu_log_mask(CPU_LOG_MMU,
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"%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
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" prot %d\n", __func__, address, ret, pa, prot);
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if (riscv_feature(env, RISCV_FEATURE_PMP) &&
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!pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << rw)) {
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ret = TRANSLATE_FAIL;
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}
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if (ret == TRANSLATE_SUCCESS) {
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tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
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prot, mmu_idx, TARGET_PAGE_SIZE);
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} else if (ret == TRANSLATE_FAIL) {
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raise_mmu_exception(env, address, rw);
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}
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#else
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switch (rw) {
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case MMU_INST_FETCH:
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cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
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break;
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case MMU_DATA_LOAD:
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cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
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break;
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case MMU_DATA_STORE:
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cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
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break;
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}
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#endif
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return ret;
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}
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/*
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* Handle Traps
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*
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* Adapted from Spike's processor_t::take_trap.
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*
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*/
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void riscv_cpu_do_interrupt(CPUState *cs)
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{
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#if !defined(CONFIG_USER_ONLY)
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RISCVCPU *cpu = RISCV_CPU(cs->uc, cs);
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CPURISCVState *env = &cpu->env;
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/* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
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* so we mask off the MSB and separate into trap type and cause.
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*/
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bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
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target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
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target_ulong deleg = async ? env->mideleg : env->medeleg;
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target_ulong tval = 0;
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static const int ecall_cause_map[] = {
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[PRV_U] = RISCV_EXCP_U_ECALL,
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[PRV_S] = RISCV_EXCP_S_ECALL,
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[PRV_H] = RISCV_EXCP_H_ECALL,
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[PRV_M] = RISCV_EXCP_M_ECALL
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};
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if (!async) {
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/* set tval to badaddr for traps with address information */
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switch (cause) {
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case RISCV_EXCP_INST_ADDR_MIS:
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case RISCV_EXCP_INST_ACCESS_FAULT:
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case RISCV_EXCP_LOAD_ADDR_MIS:
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case RISCV_EXCP_STORE_AMO_ADDR_MIS:
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case RISCV_EXCP_LOAD_ACCESS_FAULT:
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case RISCV_EXCP_STORE_AMO_ACCESS_FAULT:
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case RISCV_EXCP_INST_PAGE_FAULT:
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case RISCV_EXCP_LOAD_PAGE_FAULT:
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case RISCV_EXCP_STORE_PAGE_FAULT:
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tval = env->badaddr;
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break;
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default:
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break;
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}
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/* ecall is dispatched as one cause so translate based on mode */
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if (cause == RISCV_EXCP_U_ECALL) {
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assert(env->priv <= 3);
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cause = ecall_cause_map[env->priv];
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}
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}
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if (RISCV_DEBUG_INTERRUPT) {
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qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": %s %s, "
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"epc 0x" TARGET_FMT_lx ": tval 0x" TARGET_FMT_lx "\n",
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env->mhartid, async ? "intr" : "trap",
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(async ? riscv_intr_names : riscv_excp_names)[cause],
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env->pc, tval);
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}
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if (env->priv <= PRV_S &&
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cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
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/* handle the trap in S-mode */
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target_ulong s = env->mstatus;
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s = set_field(s, MSTATUS_SPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ?
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get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv));
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s = set_field(s, MSTATUS_SPP, env->priv);
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s = set_field(s, MSTATUS_SIE, 0);
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env->mstatus = s;
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env->scause = cause | ~(((target_ulong)-1) >> async);
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env->sepc = env->pc;
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env->sbadaddr = tval;
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env->pc = (env->stvec >> 2 << 2) +
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((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
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riscv_cpu_set_mode(env, PRV_S);
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} else {
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/* handle the trap in M-mode */
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target_ulong s = env->mstatus;
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s = set_field(s, MSTATUS_MPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ?
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get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->priv));
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s = set_field(s, MSTATUS_MPP, env->priv);
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s = set_field(s, MSTATUS_MIE, 0);
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env->mstatus = s;
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env->mcause = cause | ~(((target_ulong)-1) >> async);
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env->mepc = env->pc;
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env->mbadaddr = tval;
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env->pc = (env->mtvec >> 2 << 2) +
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((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
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riscv_cpu_set_mode(env, PRV_M);
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}
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/* TODO yield load reservation */
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#endif
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cs->exception_index = EXCP_NONE; /* mark handled to qemu */
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}
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