unicorn/qemu/target/riscv
Hesham Almatary e648455989
RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off
The current implementation returns 1 (PMP check success) if the address is in
range even if the PMP entry is off. This is a bug.

For example, if there is a PMP check in S-Mode which is in range, but its PMP
entry is off, this will succeed, which it should not.

The patch fixes this bug by only checking the PMP permissions if the address is
in range and its corresponding PMP entry it not off. Otherwise, it will keep
the ret = -1 which will be checked and handled correctly at the end of the
function.

Backports commit f8162068f18f2f264a0355938784f54089234211 from qemu
2019-08-08 16:55:52 -04:00
..
insn_trans target/riscv: Split gen_arith_imm into functional and temp 2019-05-28 19:07:53 -04:00
cpu_bits.h Supply missing header guards 2019-06-12 10:59:10 -04:00
cpu_helper.c RISC-V: Check PMP during Page Table Walks 2019-08-08 16:54:45 -04:00
cpu_user.h Supply missing header guards 2019-06-12 10:59:10 -04:00
cpu-param.h tcg: Split out target/arch/cpu-param.h 2019-06-10 19:35:46 -04:00
cpu.c target/riscv: Implement riscv_cpu_unassigned_access 2019-08-08 16:48:02 -04:00
cpu.h RISC-V: Check PMP during Page Table Walks 2019-08-08 16:54:45 -04:00
csr.c target/riscv: Use env_cpu, env_archcpu 2019-06-12 12:06:19 -04:00
fpu_helper.c
helper.h
insn16-32.decode target/riscv: Split RVC32 and RVC64 insns into separate files 2019-05-28 19:00:23 -04:00
insn16-64.decode target/riscv: Add checks for several RVC reserved operands 2019-05-28 19:20:36 -04:00
insn16.decode target/riscv: Add checks for several RVC reserved operands 2019-05-28 19:20:36 -04:00
insn32-64.decode target/riscv: Convert RV64D insns to decodetree 2019-03-18 16:57:16 -04:00
insn32.decode target/riscv: Name the argument sets for all of insn32 formats 2019-05-28 18:36:53 -04:00
instmap.h Supply missing header guards 2019-06-12 10:59:10 -04:00
Makefile.objs target/riscv: Split RVC32 and RVC64 insns into separate files 2019-05-28 19:00:23 -04:00
op_helper.c target/riscv: Use env_cpu, env_archcpu 2019-06-12 12:06:19 -04:00
pmp.c RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off 2019-08-08 16:55:52 -04:00
pmp.h RISC-V: Check for the effective memory privilege mode during PMP checks 2019-08-08 16:52:57 -04:00
translate.c target/riscv: Split gen_arith_imm into functional and temp 2019-05-28 19:07:53 -04:00
unicorn.c
unicorn.h