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shader: Implement DMNMX, DSET, DSETP

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This commit is contained in:
ameerj 2021-03-21 19:28:37 -04:00
parent 56be556eee
commit e4e1cc11b8
16 changed files with 210 additions and 59 deletions
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3
src/shader_recompiler/CMakeLists.txt
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@ -65,8 +65,11 @@ add_library(shader_recompiler STATIC
frontend/maxwell/translate/impl/common_funcs.h
frontend/maxwell/translate/impl/condition_code_set.cpp
frontend/maxwell/translate/impl/double_add.cpp
frontend/maxwell/translate/impl/double_compare_and_set.cpp
frontend/maxwell/translate/impl/double_fused_multiply_add.cpp
frontend/maxwell/translate/impl/double_min_max.cpp
frontend/maxwell/translate/impl/double_multiply.cpp
frontend/maxwell/translate/impl/double_set_predicate.cpp
frontend/maxwell/translate/impl/exit_program.cpp
frontend/maxwell/translate/impl/find_leading_one.cpp
frontend/maxwell/translate/impl/floating_point_add.cpp

39
src/shader_recompiler/backend/spirv/emit_spirv.cpp
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@ -152,24 +152,7 @@ void DefineEntryPoint(Environment& env, EmitContext& ctx, Id main) {
void SetupDenormControl(const Profile& profile, const IR::Program& program, EmitContext& ctx,
Id main_func) {
if (!profile.support_float_controls) {
return;
}
const Info& info{program.info};
if (!info.uses_fp32_denorms_flush && !info.uses_fp32_denorms_preserve &&
!info.uses_fp16_denorms_flush && !info.uses_fp16_denorms_preserve) {
return;
}
ctx.AddExtension("SPV_KHR_float_controls");
if (info.uses_fp16 && profile.support_fp16_signed_zero_nan_preserve) {
ctx.AddCapability(spv::Capability::SignedZeroInfNanPreserve);
ctx.AddExecutionMode(main_func, spv::ExecutionMode::SignedZeroInfNanPreserve, 16U);
}
if (profile.support_fp32_signed_zero_nan_preserve) {
ctx.AddCapability(spv::Capability::SignedZeroInfNanPreserve);
ctx.AddExecutionMode(main_func, spv::ExecutionMode::SignedZeroInfNanPreserve, 32U);
}
if (info.uses_fp32_denorms_flush && info.uses_fp32_denorms_preserve) {
// LOG_ERROR(HW_GPU, "Fp32 denorm flush and preserve on the same shader");
} else if (info.uses_fp32_denorms_flush) {
@ -210,6 +193,22 @@ void SetupDenormControl(const Profile& profile, const IR::Program& program, Emit
}
}
void SetupSignedNanCapabilities(const Profile& profile, const IR::Program& program,
EmitContext& ctx, Id main_func) {
if (program.info.uses_fp16 && profile.support_fp16_signed_zero_nan_preserve) {
ctx.AddCapability(spv::Capability::SignedZeroInfNanPreserve);
ctx.AddExecutionMode(main_func, spv::ExecutionMode::SignedZeroInfNanPreserve, 16U);
}
if (profile.support_fp32_signed_zero_nan_preserve) {
ctx.AddCapability(spv::Capability::SignedZeroInfNanPreserve);
ctx.AddExecutionMode(main_func, spv::ExecutionMode::SignedZeroInfNanPreserve, 32U);
}
if (program.info.uses_fp64 && profile.support_fp64_signed_zero_nan_preserve) {
ctx.AddCapability(spv::Capability::SignedZeroInfNanPreserve);
ctx.AddExecutionMode(main_func, spv::ExecutionMode::SignedZeroInfNanPreserve, 64U);
}
}
void SetupCapabilities(const Profile& profile, const Info& info, EmitContext& ctx) {
if (info.uses_sampled_1d) {
ctx.AddCapability(spv::Capability::Sampled1D);
@ -260,7 +259,11 @@ std::vector<u32> EmitSPIRV(const Profile& profile, Environment& env, IR::Program
EmitContext ctx{profile, program, binding};
const Id main{DefineMain(ctx, program)};
DefineEntryPoint(env, ctx, main);
SetupDenormControl(profile, program, ctx, main);
if (profile.support_float_controls) {
ctx.AddExtension("SPV_KHR_float_controls");
SetupDenormControl(profile, program, ctx, main);
SetupSignedNanCapabilities(profile, program, ctx, main);
}
SetupCapabilities(profile, program.info, ctx);
return ctx.Assemble();
}

1
src/shader_recompiler/backend/spirv/emit_spirv.h
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@ -136,6 +136,7 @@ Id EmitSelectU32(EmitContext& ctx, Id cond, Id true_value, Id false_value);
Id EmitSelectU64(EmitContext& ctx, Id cond, Id true_value, Id false_value);
Id EmitSelectF16(EmitContext& ctx, Id cond, Id true_value, Id false_value);
Id EmitSelectF32(EmitContext& ctx, Id cond, Id true_value, Id false_value);
Id EmitSelectF64(EmitContext& ctx, Id cond, Id true_value, Id false_value);
void EmitBitCastU16F16(EmitContext& ctx);
Id EmitBitCastU32F32(EmitContext& ctx, Id value);
void EmitBitCastU64F64(EmitContext& ctx);

4
src/shader_recompiler/backend/spirv/emit_spirv_select.cpp
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@ -35,4 +35,8 @@ Id EmitSelectF32(EmitContext& ctx, Id cond, Id true_value, Id false_value) {
return ctx.OpSelect(ctx.F32[1], cond, true_value, false_value);
}
Id EmitSelectF64(EmitContext& ctx, Id cond, Id true_value, Id false_value) {
return ctx.OpSelect(ctx.F64[1], cond, true_value, false_value);
}
} // namespace Shader::Backend::SPIRV

2
src/shader_recompiler/frontend/ir/ir_emitter.cpp
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@ -529,6 +529,8 @@ Value IREmitter::Select(const U1& condition, const Value& true_value, const Valu
return Inst(Opcode::SelectU64, condition, true_value, false_value);
case Type::F32:
return Inst(Opcode::SelectF32, condition, true_value, false_value);
case Type::F64:
return Inst(Opcode::SelectF64, condition, true_value, false_value);
default:
throw InvalidArgument("Invalid type {}", true_value.Type());
}

1
src/shader_recompiler/frontend/ir/opcodes.inc
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@ -131,6 +131,7 @@ OPCODE(SelectU32, U32, U1,
OPCODE(SelectU64, U64, U1, U64, U64, )
OPCODE(SelectF16, F16, U1, F16, F16, )
OPCODE(SelectF32, F32, U1, F32, F32, )
OPCODE(SelectF64, F64, U1, F64, F64, )
// Bitwise conversions
OPCODE(BitCastU16F16, U16, F16, )

4
src/shader_recompiler/frontend/maxwell/maxwell.inc
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@ -37,8 +37,8 @@ INST(DFMA_reg, "DFMA (reg)", "0101 1011 0111 ----")
INST(DFMA_rc, "DFMA (rc)", "0101 0011 0111 ----")
INST(DFMA_cr, "DFMA (cr)", "0100 1011 0111 ----")
INST(DFMA_imm, "DFMA (imm)", "0011 011- 0111 ----")
INST(DMNMX_reg, "DMNMX (reg)", "0100 1100 0101 0---")
INST(DMNMX_cbuf, "DMNMX (cbuf)", "0101 1100 0101 0---")
INST(DMNMX_reg, "DMNMX (reg)", "0101 1100 0101 0---")
INST(DMNMX_cbuf, "DMNMX (cbuf)", "0100 1100 0101 0---")
INST(DMNMX_imm, "DMNMX (imm)", "0011 100- 0101 0---")
INST(DMUL_reg, "DMUL (reg)", "0101 1100 1000 0---")
INST(DMUL_cbuf, "DMUL (cbuf)", "0100 1100 1000 0---")

59
src/shader_recompiler/frontend/maxwell/translate/impl/double_compare_and_set.cpp Normal file
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@ -0,0 +1,59 @@
// Copyright 2021 yuzu Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#include "common/bit_field.h"
#include "common/common_types.h"
#include "shader_recompiler/frontend/maxwell/translate/impl/common_funcs.h"
#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
namespace Shader::Maxwell {
namespace {
void DSET(TranslatorVisitor& v, u64 insn, const IR::F64& src_b) {
union {
u64 insn;
BitField<0, 8, IR::Reg> dest_reg;
BitField<8, 8, IR::Reg> src_a_reg;
BitField<39, 3, IR::Pred> pred;
BitField<42, 1, u64> neg_pred;
BitField<43, 1, u64> negate_a;
BitField<44, 1, u64> abs_b;
BitField<45, 2, BooleanOp> bop;
BitField<48, 4, FPCompareOp> compare_op;
BitField<52, 1, u64> bf;
BitField<53, 1, u64> negate_b;
BitField<54, 1, u64> abs_a;
} const dset{insn};
const IR::F64 op_a{v.ir.FPAbsNeg(v.D(dset.src_a_reg), dset.abs_a != 0, dset.negate_a != 0)};
const IR::F64 op_b{v.ir.FPAbsNeg(src_b, dset.abs_b != 0, dset.negate_b != 0)};
IR::U1 pred{v.ir.GetPred(dset.pred)};
if (dset.neg_pred != 0) {
pred = v.ir.LogicalNot(pred);
}
const IR::U1 cmp_result{FloatingPointCompare(v.ir, op_a, op_b, dset.compare_op)};
const IR::U1 bop_result{PredicateCombine(v.ir, cmp_result, pred, dset.bop)};
const IR::U32 one_mask{v.ir.Imm32(-1)};
const IR::U32 fp_one{v.ir.Imm32(0x3f800000)};
const IR::U32 fail_result{v.ir.Imm32(0)};
const IR::U32 pass_result{dset.bf == 0 ? one_mask : fp_one};
v.X(dset.dest_reg, IR::U32{v.ir.Select(bop_result, pass_result, fail_result)});
}
} // Anonymous namespace
void TranslatorVisitor::DSET_reg(u64 insn) {
DSET(*this, insn, GetDoubleReg20(insn));
}
void TranslatorVisitor::DSET_cbuf(u64 insn) {
DSET(*this, insn, GetDoubleCbuf(insn));
}
void TranslatorVisitor::DSET_imm(u64 insn) {
DSET(*this, insn, GetDoubleImm20(insn));
}
} // namespace Shader::Maxwell

50
src/shader_recompiler/frontend/maxwell/translate/impl/double_min_max.cpp Normal file
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@ -0,0 +1,50 @@
// Copyright 2021 yuzu Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#include "common/bit_field.h"
#include "common/common_types.h"
#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
namespace Shader::Maxwell {
namespace {
void DMNMX(TranslatorVisitor& v, u64 insn, const IR::F64& src_b) {
union {
u64 insn;
BitField<0, 8, IR::Reg> dest_reg;
BitField<8, 8, IR::Reg> src_a_reg;
BitField<39, 3, IR::Pred> pred;
BitField<42, 1, u64> neg_pred;
BitField<45, 1, u64> negate_b;
BitField<46, 1, u64> abs_a;
BitField<48, 1, u64> negate_a;
BitField<49, 1, u64> abs_b;
} const dmnmx{insn};
const IR::U1 pred{v.ir.GetPred(dmnmx.pred)};
const IR::F64 op_a{v.ir.FPAbsNeg(v.D(dmnmx.src_a_reg), dmnmx.abs_a != 0, dmnmx.negate_a != 0)};
const IR::F64 op_b{v.ir.FPAbsNeg(src_b, dmnmx.abs_b != 0, dmnmx.negate_b != 0)};
IR::F64 max{v.ir.FPMax(op_a, op_b)};
IR::F64 min{v.ir.FPMin(op_a, op_b)};
if (dmnmx.neg_pred != 0) {
std::swap(min, max);
}
v.D(dmnmx.dest_reg, IR::F64{v.ir.Select(pred, min, max)});
}
} // Anonymous namespace
void TranslatorVisitor::DMNMX_reg(u64 insn) {
DMNMX(*this, insn, GetDoubleReg20(insn));
}
void TranslatorVisitor::DMNMX_cbuf(u64 insn) {
DMNMX(*this, insn, GetDoubleCbuf(insn));
}
void TranslatorVisitor::DMNMX_imm(u64 insn) {
DMNMX(*this, insn, GetDoubleImm20(insn));
}
} // namespace Shader::Maxwell

54
src/shader_recompiler/frontend/maxwell/translate/impl/double_set_predicate.cpp Normal file
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@ -0,0 +1,54 @@
// Copyright 2021 yuzu Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#include "common/bit_field.h"
#include "common/common_types.h"
#include "shader_recompiler/frontend/maxwell/translate/impl/common_funcs.h"
#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
namespace Shader::Maxwell {
namespace {
void DSETP(TranslatorVisitor& v, u64 insn, const IR::F64& src_b) {
union {
u64 insn;
BitField<0, 3, IR::Pred> dest_pred_b;
BitField<3, 3, IR::Pred> dest_pred_a;
BitField<6, 1, u64> negate_b;
BitField<7, 1, u64> abs_a;
BitField<8, 8, IR::Reg> src_a_reg;
BitField<39, 3, IR::Pred> bop_pred;
BitField<42, 1, u64> neg_bop_pred;
BitField<43, 1, u64> negate_a;
BitField<44, 1, u64> abs_b;
BitField<45, 2, BooleanOp> bop;
BitField<48, 4, FPCompareOp> compare_op;
} const dsetp{insn};
const IR::F64 op_a{v.ir.FPAbsNeg(v.D(dsetp.src_a_reg), dsetp.abs_a != 0, dsetp.negate_a != 0)};
const IR::F64 op_b{v.ir.FPAbsNeg(src_b, dsetp.abs_b != 0, dsetp.negate_b != 0)};
const BooleanOp bop{dsetp.bop};
const FPCompareOp compare_op{dsetp.compare_op};
const IR::U1 comparison{FloatingPointCompare(v.ir, op_a, op_b, compare_op)};
const IR::U1 bop_pred{v.ir.GetPred(dsetp.bop_pred, dsetp.neg_bop_pred != 0)};
const IR::U1 result_a{PredicateCombine(v.ir, comparison, bop_pred, bop)};
const IR::U1 result_b{PredicateCombine(v.ir, v.ir.LogicalNot(comparison), bop_pred, bop)};
v.ir.SetPred(dsetp.dest_pred_a, result_a);
v.ir.SetPred(dsetp.dest_pred_b, result_b);
}
} // Anonymous namespace
void TranslatorVisitor::DSETP_reg(u64 insn) {
DSETP(*this, insn, GetDoubleReg20(insn));
}
void TranslatorVisitor::DSETP_cbuf(u64 insn) {
DSETP(*this, insn, GetDoubleCbuf(insn));
}
void TranslatorVisitor::DSETP_imm(u64 insn) {
DSETP(*this, insn, GetDoubleImm20(insn));
}
} // namespace Shader::Maxwell

2
src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_min_max.cpp
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@ -24,7 +24,7 @@ void FMNMX(TranslatorVisitor& v, u64 insn, const IR::F32& src_b) {
const IR::U1 pred{v.ir.GetPred(fmnmx.pred)};
const IR::F32 op_a{v.ir.FPAbsNeg(v.F(fmnmx.src_a_reg), fmnmx.abs_a != 0, fmnmx.negate_a != 0)};
const IR::F32 op_b = v.ir.FPAbsNeg(src_b, fmnmx.abs_b != 0, fmnmx.negate_b != 0);
const IR::F32 op_b{v.ir.FPAbsNeg(src_b, fmnmx.abs_b != 0, fmnmx.negate_b != 0)};
const IR::FpControl control{
.no_contraction{false},

36
src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
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@ -81,42 +81,6 @@ void TranslatorVisitor::DEPBAR() {
// DEPBAR is a no-op
}
void TranslatorVisitor::DMNMX_reg(u64) {
ThrowNotImplemented(Opcode::DMNMX_reg);
}
void TranslatorVisitor::DMNMX_cbuf(u64) {
ThrowNotImplemented(Opcode::DMNMX_cbuf);
}
void TranslatorVisitor::DMNMX_imm(u64) {
ThrowNotImplemented(Opcode::DMNMX_imm);
}
void TranslatorVisitor::DSET_reg(u64) {
ThrowNotImplemented(Opcode::DSET_reg);
}
void TranslatorVisitor::DSET_cbuf(u64) {
ThrowNotImplemented(Opcode::DSET_cbuf);
}
void TranslatorVisitor::DSET_imm(u64) {
ThrowNotImplemented(Opcode::DSET_imm);
}
void TranslatorVisitor::DSETP_reg(u64) {
ThrowNotImplemented(Opcode::DSETP_reg);
}
void TranslatorVisitor::DSETP_cbuf(u64) {
ThrowNotImplemented(Opcode::DSETP_cbuf);
}
void TranslatorVisitor::DSETP_imm(u64) {
ThrowNotImplemented(Opcode::DSETP_imm);
}
void TranslatorVisitor::FCHK_reg(u64) {
ThrowNotImplemented(Opcode::FCHK_reg);
}

1
src/shader_recompiler/ir_opt/collect_shader_info_pass.cpp
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@ -130,6 +130,7 @@ void VisitUsages(Info& info, IR::Inst& inst) {
case IR::Opcode::CompositeInsertF64x2:
case IR::Opcode::CompositeInsertF64x3:
case IR::Opcode::CompositeInsertF64x4:
case IR::Opcode::SelectF64:
case IR::Opcode::BitCastU64F64:
case IR::Opcode::BitCastF64U64:
case IR::Opcode::PackDouble2x32:

10
src/shader_recompiler/ir_opt/constant_propagation_pass.cpp
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@ -229,7 +229,6 @@ void FoldISub32(IR::Inst& inst) {
}
}
template <typename T>
void FoldSelect(IR::Inst& inst) {
const IR::Value cond{inst.Arg(0)};
if (cond.IsImmediate()) {
@ -340,8 +339,15 @@ void ConstantPropagation(IR::Block& block, IR::Inst& inst) {
return FoldBitCast<IR::Opcode::BitCastU32F32, u32, f32>(inst, IR::Opcode::BitCastF32U32);
case IR::Opcode::IAdd64:
return FoldAdd<u64>(block, inst);
case IR::Opcode::SelectU1:
case IR::Opcode::SelectU8:
case IR::Opcode::SelectU16:
case IR::Opcode::SelectU32:
return FoldSelect<u32>(inst);
case IR::Opcode::SelectU64:
case IR::Opcode::SelectF16:
case IR::Opcode::SelectF32:
case IR::Opcode::SelectF64:
return FoldSelect(inst);
case IR::Opcode::LogicalAnd:
return FoldLogicalAnd(inst);
case IR::Opcode::LogicalOr:

1
src/shader_recompiler/profile.h
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@ -18,6 +18,7 @@ struct Profile {
bool support_fp32_denorm_flush{};
bool support_fp16_signed_zero_nan_preserve{};
bool support_fp32_signed_zero_nan_preserve{};
bool support_fp64_signed_zero_nan_preserve{};
// FClamp is broken and OpFMax + OpFMin should be used instead
bool has_broken_spirv_clamp{};

2
src/video_core/renderer_vulkan/vk_pipeline_cache.cpp
View File

@ -244,6 +244,8 @@ PipelineCache::PipelineCache(RasterizerVulkan& rasterizer_, Tegra::GPU& gpu_,
float_control.shaderSignedZeroInfNanPreserveFloat16 != VK_FALSE,
.support_fp32_signed_zero_nan_preserve =
float_control.shaderSignedZeroInfNanPreserveFloat32 != VK_FALSE,
.support_fp64_signed_zero_nan_preserve =
float_control.shaderSignedZeroInfNanPreserveFloat64 != VK_FALSE,
.has_broken_spirv_clamp = driver_id == VK_DRIVER_ID_INTEL_PROPRIETARY_WINDOWS_KHR,
};
}