ReinUsesLisp
a87b16da9a
shader/texture: Remove type mismatches management from shader decoder
...
Since commit e22816a5bb
we handle type mismatches from the CPU.
We don't need to hack our shader decoder due to game bugs anymore.
Removed in this commit.
2020-04-10 00:57:32 -03:00
bunnei
b96fd0bd0e
Merge pull request #3601 from ReinUsesLisp/some-shader-encodings
...
video_core/shader: Add some instruction and S2R encodings
2020-04-09 00:17:39 -04:00
Rodrigo Locatti
487f9ba525
Merge pull request #3489 from namkazt/patch-2
...
shader: implement SULD.D bits32/64
2020-04-07 16:21:09 -03:00
Nguyen Dac Nam
935648ffa9
address nit.
2020-04-07 18:29:30 +07:00
Nguyen Dac Nam
bf1174c114
Apply suggestions from code review
...
Co-Authored-By: Rodrigo Locatti <reinuseslisp@airmail.cc>
2020-04-07 07:55:49 +07:00
namkazy
2c98e14d13
shader_decode: SULD.D using std::pair instead of out parameter
2020-04-06 13:46:55 +07:00
namkazy
9efa51311f
shader_decode: SULD.D avoid duplicate code block.
2020-04-06 13:34:06 +07:00
namkazy
7f5696513f
shader_decode: SULD.D fix conversion error.
2020-04-06 13:26:58 +07:00
namkazy
2906372ba1
shader_decode: SULD.D implement bits64 and reverse shader ir init method to removed shader stage.
2020-04-06 13:09:19 +07:00
Fernando Sahmkow
69277de29d
Merge pull request #3592 from ReinUsesLisp/ipa
...
shader_decompiler: Remove FragCoord.w hack and change IPA implementation
2020-04-05 19:29:40 -04:00
namkazy
730f9b55b3
silent warning (conversion error)
2020-04-05 16:02:07 +07:00
namkazy
9f6ebccf06
shader_decode: SULD.D -> SINT actually same as UNORM.
2020-04-05 15:18:42 +07:00
namkazy
6f2b7087c2
shader_decode: SULD.D fix decode SNORM component
2020-04-05 14:46:43 +07:00
namkazy
69657ff19c
clang-format
2020-04-05 12:57:50 +07:00
namkazy
24cc64c5b3
shader_decode: get sampler descriptor from registry.
2020-04-05 12:54:48 +07:00
namkazy
acd3f0ab37
tweaking.
2020-04-05 10:31:32 +07:00
namkazy
3e3afa9be6
cleanup unuse params
2020-04-05 10:31:31 +07:00
namkazy
5cd5857000
cleanup debug code.
2020-04-05 10:31:30 +07:00
namkazy
658112783d
reimplement get component type, uncomment mistaken code
2020-04-05 10:31:30 +07:00
namkazy
3ad06e9b2b
remove disable optimize
2020-04-05 10:31:30 +07:00
namkazy
f24c2e1103
[wip] reimplement SULD.D
2020-04-05 10:31:29 +07:00
Nguyen Dac Nam
2cefdd92bd
clang-fix
2020-04-05 10:31:28 +07:00
Nguyen Dac Nam
1f3d142875
shader: image - import PredCondition
2020-04-05 10:31:27 +07:00
Nguyen Dac Nam
08db60392d
shader: SULD.D bits32 implement more complexer method.
2020-04-05 10:31:27 +07:00
Nguyen Dac Nam
ed1d8beb13
shader: SULD.D import StoreType
2020-04-05 10:31:26 +07:00
Nguyen Dac Nam
6d235b8631
shader: implement SULD.D bits32
2020-04-05 10:31:26 +07:00
ReinUsesLisp
60106531b4
shader/other: Add error message for some S2R registers
2020-04-04 03:46:07 -03:00
ReinUsesLisp
8b719e9e1d
shader_bytecode: Rename MOV_SYS to S2R
2020-04-04 03:37:51 -03:00
ReinUsesLisp
e1bd89e1c2
shader/memory: Silence no return value warning
...
Silences a warning about control paths not all returning a value.
2020-04-02 03:34:27 -03:00
ReinUsesLisp
2339fe199f
shader_decompiler: Remove FragCoord.w hack and change IPA implementation
...
Credits go to gdkchan and Ryujinx. The pull request used for this can
be found here: https://github.com/Ryujinx/Ryujinx/pull/1082
yuzu was already using the header for interpolation, but it was missing
the FragCoord.w multiplication described in the linked pull request.
This commit finally removes the FragCoord.w == 1.0f hack from the shader
decompiler.
While we are at it, this commit renames some enumerations to match
Nvidia's documentation (linked below) and fixes component declaration
order in the shader program header (z and w were swapped).
https://github.com/NVIDIA/open-gpu-doc/blob/master/Shader-Program-Header/Shader-Program-Header.html
2020-04-01 21:48:55 -03:00
Fernando Sahmkow
b03c0536ce
Merge pull request #3561 from ReinUsesLisp/f2f-conversion
...
shader/conversion: Fix F2F rounding operations with different sizes
2020-03-31 14:45:02 -04:00
Fernando Sahmkow
5b95a01463
Merge pull request #3577 from ReinUsesLisp/lea
...
shader/lea: Fix LEA implementation
2020-03-31 14:36:07 -04:00
Nguyen Dac Nam
238c35b2c9
clang-format
2020-03-31 08:08:06 +07:00
Nguyen Dac Nam
defb9642da
shader_decode: fix by suggestion
2020-03-31 08:02:44 +07:00
namkazy
cb0a4151f8
clang-format
2020-03-30 20:46:21 +07:00
namkazy
4f7bea403a
shader_decode: ATOM/ATOMS: add function to avoid code repetition
2020-03-30 18:47:50 +07:00
Nguyen Dac Nam
972485ff18
shader_decode: implement ATOM operation for S32 and U32
2020-03-30 17:44:48 +07:00
namkazy
93cac0d294
clang-format
2020-03-30 17:44:48 +07:00
Nguyen Dac Nam
3dc09a6250
shader_decode: implement ATOMS instr partial.
2020-03-30 17:44:46 +07:00
ReinUsesLisp
5300a918c6
shader/lea: Simplify generated LEA code
2020-03-28 03:55:04 -03:00
ReinUsesLisp
523a709bf1
shader/lea: Fix op_a and op_b usages
...
They were swapped.
2020-03-27 18:37:20 -03:00
ReinUsesLisp
796b3319e6
shader/lea: Remove const and use move when possible
2020-03-27 18:36:38 -03:00
ReinUsesLisp
46791c464a
shader/conversion: Fix F2F rounding operations with different sizes
...
Rounding operations only matter when the conversion size of source and
destination is the same, i.e. .F16.F16, .F32.F32 and .F64.F64.
When there is a mismatch (.F16.F32), these bits are used for IEEE
rounding, we don't emulate this because GLSL and SPIR-V don't support
configuring it per operation.
2020-03-26 01:58:49 -03:00
makigumo
5a5c6d4ed8
xmad: fix clang build error
2020-03-23 00:09:31 +01:00
bunnei
bdddbe2daa
Merge pull request #3505 from namkazt/patch-8
...
shader_decode: implement XMAD mode CSfu
2020-03-19 17:41:01 -04:00
Rodrigo Locatti
ddafc99776
Merge pull request #3502 from namkazt/patch-3
...
shader_decode: Reimplement BFE instructions
2020-03-15 21:23:04 -03:00
Nguyen Dac Nam
3287b1247d
clang-format
2020-03-14 10:07:40 +07:00
Nguyen Dac Nam
240d45830d
nit
2020-03-14 09:57:24 +07:00
Nguyen Dac Nam
829f424618
nit & remove some optional param
2020-03-13 20:47:38 +07:00
Nguyen Dac Nam
a166217480
shader_decode: implement XMAD mode CSfu
2020-03-13 19:01:49 +07:00