Commit Graph

4367 Commits

Author SHA1 Message Date
Alex Bennée
4ea310c131
arm/translate-a64: add FP16 FRECPE
Now we have added f16 during the re-factoring we can simply call the
helper.

Backports commit fbd06e1e4b6566b4d727f9e553c819d034942f68 from qemu
2018-03-08 19:12:06 -05:00
Alex Bennée
5f3864c2c2
arm/helper.c: re-factor recpe and add recepe_f16
It looks like the ARM ARM has simplified the pseudo code for the
calculation which is done on a fixed point 9 bit integer maths. So
while adding f16 we can also clean this up to be a little less heavy
on the floating point and just return the fractional part and leave
the calle's to do the final packing of the result.

Backports commit 5eb70735af1c0b607bf2671a53aff3710cc1672f from qemu
2018-03-08 19:05:48 -05:00
Alex Bennée
c590ff441c
arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
Neither of these operations alter the floating point status registers
so we can do a pure bitwise operation, either squashing any sign
bit (ABS) or inverting it (NEG).

Backports commit 15f8a233c8c023dbc77b6fe6cd7c79eac9bee263 from qemu
2018-03-08 18:51:35 -05:00
Alex Bennée
7161c1ed52
arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16 2018-03-08 18:48:25 -05:00
Alex Bennée
8ac9e3cff2
arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
I re-use the existing handle_2misc_fcmp_zero handler and tweak it
slightly to deal with the half-precision case.

Backports commit 7d4dd1a73a023f75c893623710e43743501b318e from qemu
2018-03-08 18:32:36 -05:00
Alex Bennée
39a68548d1
arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
This covers all the floating point convert operations.

Backports commit 2df581304193d70eaf0d22cf4cb4613f74b6e59b from qemu
2018-03-08 18:25:29 -05:00
Alex Bennée
d5f002b39a
arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
This adds the full range of half-precision floating point to integral
instructions.

Backports commit 6109aea2d954891027acba64a13f1f1c7463cfac from qemu
2018-03-08 18:21:58 -05:00
Alex Bennée
33eda0f5d4
arm/translate-a64: initial decode for simd_two_reg_misc_fp16
This actually covers two different sections of the encoding table:

Advanced SIMD scalar two-register miscellaneous FP16
Advanced SIMD two-register miscellaneous (FP16)

The difference between the two is covered by a combination of Q (bit
30) and S (bit 28). Notably the FRINTx instructions are only
available in the vector form.

This is just the decode skeleton which will be filled out by later
patches.

Backports commit 5d432be6fd6efe37833ac82623c3abd35117b421 from qemu
2018-03-08 18:14:04 -05:00
Alex Bennée
82ffaab7de
arm/translate-a64: add FP16 x2 ops for simd_indexed
A bunch of the vectorised bitwise operations just operate on larger
chunks at a time. We can do the same for the new half-precision
operations by introducing some TWOHALFOP helpers which work on each
half of a pair of half-precision operations at once.

Hopefully all this hoop jumping will get simpler once we have
generically vectorised helpers here.

Backports commit 6089030c7322d8f96b54fb9904e53b0f464bb8fe from qemu
2018-03-08 18:08:39 -05:00
Alex Bennée
38815b2901
arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
The helpers use the new re-factored muladd support in SoftFloat for
the float16 work.

Backports commit 5d265064cf30daaacce5a4ce9945fc573015fb5f from qemu
2018-03-08 15:56:20 -05:00
Alex Bennée
c6fda07628
arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
This includes FMAXNMP, FADDP, FMAXP, FMINNMP, FMINP.

Backports commit 7a2c6e618156674cf9eac8bf36e79f674fbf974e from qemu
2018-03-08 15:50:56 -05:00
Alex Bennée
4b2577537b
arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
As some of the constants here will also be needed
elsewhere (specifically for the upcoming SVE support) we move them out
to softfloat.h.

Backports commit 026e2d6ef74000afb9049f46add4b94f594c8fb3 from qemu
2018-03-08 15:47:34 -05:00
Alex Bennée
a02b9b81a9
arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
Backports commit 2deb992b767d28035fac3b374c7730494ff0b43d from qemu

Also backports the fp16 changes introduced in commit f566c0474a9b9bbd9ed248607e4007e24d3358c0
2018-03-08 15:42:48 -05:00
Alex Bennée
ba8df54753
arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16
These use the generic float16_compare functionality which in turn uses
the common float_compare code from the softfloat re-factor.

Backports commit d32adeae1a71a8e71374fa48d3d6ab0ad4c23e94 from qemu
2018-03-08 12:59:37 -05:00
Alex Bennée
4a6a41d2c5
arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16
The fprintf is only there for debugging as the skeleton is added to,
it will be removed once the skeleton is complete.

Backports commit 372087348d561e7f4051d7b32609bda417092ddf from qemu
2018-03-08 12:56:15 -05:00
Alex Bennée
2f850606e9
arm/translate-a64: initial decode for simd_three_reg_same_fp16
This is the initial decode skeleton for the Advanced SIMD three same
instruction group.

The fprintf is purely to aid debugging as the additional instructions
are added. It will be removed once the group is complete.

Backports commit 376e8d6cda985df31c8561db4b7ea365b6fe6f87 from qemu
2018-03-08 12:53:23 -05:00
Alex Bennée
fe74abd307
arm/translate-a64: handle_3same_64 comment fix
We do implement all the opcodes.

Backports commit 3840d219b433507f04a685120ff770ce4e06c55d from qemu
2018-03-08 12:51:01 -05:00
Alex Bennée
af75074fe7
arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
This implements the half-precision variants of the across vector
reduction operations. This involves a re-factor of the reduction code
which more closely matches the ARM ARM order (and handles 8 element
reductions).

Backports commit 807cdd504283c11addcd7ea95ba594bbddc86fe4 from qemu
2018-03-08 12:49:30 -05:00
Alex Bennée
27d8d01566
target/arm/helper: pass explicit fpst to set_rmode
As the rounding mode is now split between FP16 and the rest of
floating point we need to be explicit when tweaking it. Instead of
passing the CPU env we now pass the appropriate fpst pointer directly.

Backports commit 9b04991686785e18b18a36d193b68f08f7c91648 from qemu
2018-03-08 12:41:54 -05:00
Alex Bennée
996f38056f
target/arm/cpu.h: add additional float_status flags
Half-precision flush to zero behaviour is controlled by a separate
FZ16 bit in the FPCR. To handle this we pass a pointer to
fp_status_fp16 when working on half-precision operations. The value of
the presented FPCR is calculated from an amalgam of the two when read.

Backports commit d81ce0ef2c4f1052fcdef891a12499eca3084db7 from qemu
2018-03-08 12:34:39 -05:00
Alex Bennée
348789d2e4
target/arm/cpu.h: update comment for half-precision values
Backports commit d0e69ea88f4e74212b29d9436143c5bcfd437757 from qemu
2018-03-08 12:29:47 -05:00
Alex Bennée
a030564492
target/arm/cpu64: introduce ARM_V8_FP16 feature bit
Backports commit 6ad4d6187563f069fe5f11c3c1c9ccec1f69c2b7 from qemu
2018-03-08 12:29:17 -05:00
Alex Bennée
e56ed38819
include/exec/helper-head.h: support f16 in helper calls
This allows us to explicitly pass float16 to helpers rather than
assuming uint32_t and dealing with the result. Of course they will be
passed in i32 sized registers by default.

Backports commit 35737497008aeabce5dc381a41d3827bec486192 from qemu
2018-03-08 12:28:05 -05:00
Peter Maydell
f4df29ca4f
target/arm: Fix register definitions for VMIDR and VMPIDR
The register definitions for VMIDR and VMPIDR have separate
reginfo structs for the AArch32 and AArch64 registers. However
the 32-bit versions are wrong:
* they use offsetof instead of offsetoflow32 to mark where
the 32-bit value lives in the uint64_t CPU state field
* they don't mark themselves as ARM_CP_ALIAS

In particular this means that if you try to use an Arm guest CPU
which enables EL2 on a big-endian host it will assert at reset:
target/arm/cpu.c:114: cp_reg_check_reset: Assertion `oldvalue == newvalue' failed.

because the reset of the 32-bit register writes to the top
half of the uint64_t.

Correct the errors in the structures.

Backports commit 36476562d57a3b64bbe86db26e63677dd21907c5 from qemu
2018-03-08 12:26:09 -05:00
Alex Bennée
283abedc68
fpu/softfloat: re-factor sqrt
This is a little bit of a departure from softfloat's original approach
as we skip the estimate step in favour of a straight iteration. There
is a minor optimisation to avoid calculating more bits of precision
than we need however this still brings a performance drop, especially
for float64 operations.

Backports commit c13bb2da9eedfbc5886c8048df1bc1114b285fb0 from qemu
2018-03-08 12:23:54 -05:00
Alex Bennée
e2fb4b40c3
fpu/softfloat: re-factor compare
The compare function was already expanded from a macro. I keep the
macro expansion but move most of the logic into a compare_decomposed.

Backports commit 0c4c90929143a530730e2879204a55a30bf63758 from qemu
2018-03-08 12:21:20 -05:00
Alex Bennée
c38b64f8a9
fpu/softfloat: re-factor minmax
Let's do the same re-factor treatment for minmax functions. I still
use the MACRO trick to expand but now all the checking code is common.

Backports commit 89360067071b1844bf745682e18db7dde74cdb8d from qemu
2018-03-08 12:18:35 -05:00
Alex Bennée
9b296329f6
fpu/softfloat: re-factor scalbn
This is one of the simpler manipulations you could make to a floating
point number.

Backports commit 0bfc9f195209593e91a98cf2233753f56a2e5c02 from qemu
2018-03-08 12:16:19 -05:00
Alex Bennée
b389a8c7c4
fpu/softfloat: re-factor int/uint to float
These are considerably simpler as the lower order integers can just
use the higher order conversion function. As the decomposed fractional
part is a full 64 bit rounding and inexact handling comes from the
pack functions.

Backports commit c02e1fb80b553d47420f7492de4bc590c2461a86 from qemu
2018-03-08 12:13:09 -05:00
Alex Bennée
acb4b1d5b1
fpu/softfloat: re-factor float to int/uint
We share the common int64/uint64_pack_decomposed function across all
the helpers and simply limit the final result depending on the final
size.

Backports commit ab52f973a504f8de0c5df64631ba4caea70a7d9e from qemu
2018-03-08 12:07:20 -05:00
Alex Bennée
b82253adce
fpu/softfloat: re-factor round_to_int
We can now add float16_round_to_int and use the common round_decomposed and
canonicalize functions to have a single implementation for
float16/32/64 round_to_int functions.

Backports commit dbe4d53a590f5689772b683984588b3cf6df163e from qemu
2018-03-08 11:56:59 -05:00
Alex Bennée
d92d5c6910
fpu/softfloat: re-factor muladd
We can now add float16_muladd and use the common decompose and
canonicalize functions to have a single implementation for
float16/32/64 muladd functions.

Backports commit d446830a3aac33e7221e361dad3ab1e1892646cb from qemu
2018-03-08 10:55:40 -05:00
Alex Bennée
5ea008e178
fpu/softfloat: re-factor div
We can now add float16_div and use the common decompose and
canonicalize functions to have a single implementation for
float16/32/64 versions.

Backports commit cf07323d494f4bc225e405688c2e455c3423cc40 from qemu
2018-03-08 10:25:07 -05:00
Alex Bennée
2bb86e1efc
fpu/softfloat: re-factor mul
We can now add float16_mul and use the common decompose and
canonicalize functions to have a single implementation for
float16/32/64 versions.

Backports commit 74d707e2cc1e406068acad8e5559cd2584b1073a from qemu
2018-03-08 10:21:15 -05:00
Alex Bennée
58defd9bc0
fpu/softfloat: re-factor add/sub
We can now add float16_add/sub and use the common decompose and
canonicalize functions to have a single implementation for
float16/32/64 add and sub functions.

Backports commit 6fff216769cf7eaa3961c85dee7a72838696d365 from qemu
2018-03-08 10:17:41 -05:00
Alex Bennée
b1884d0685
fpu/softfloat: re-factor add/sub
We can now add float16_add/sub and use the common decompose and
canonicalize functions to have a single implementation for
float16/32/64 add and sub functions.

Backports commit 6fff216769cf7eaa3961c85dee7a72838696d365 from qemu
2018-03-08 10:13:14 -05:00
Alex Bennée
d80f1ea222
fpu/softfloat: define decompose structures
These structures pave the way for generic softfloat helper routines
that will operate on fully decomposed numbers.

Backports commit a90119b5a2c174250601be6503b91e5c9df6e83b from qemu
2018-03-08 10:06:25 -05:00
Alex Bennée
562f14adcc
fpu/softfloat: move the extract functions to the top of the file
This is pure code-motion during re-factoring as the helpers will be
needed earlier.

Backports commit d97544c94a37371347402bcbee19dd3748d70e48 from qemu
2018-03-08 10:04:54 -05:00
Alex Bennée
b5fdc7b411
fpu/softfloat: improve comments on ARM NaN propagation
Mention the pseudo-code fragment from which this is based.

Backports commit 13894527f522caab4ec74334191ef29af975e521 from qemu
2018-03-08 10:03:32 -05:00
Alex Bennée
6eb4594f98
include/fpu/softfloat: add some float16 constants
This defines the same set of common constants for float 16 as defined
for 32 and 64 bit floats. These are often used by target helper
functions. I've also removed constants that are not used by anybody.

Backports commit efd4829edfa036c5506a16d05c91268faa1f6332 from qemu
2018-03-08 10:02:26 -05:00
Alex Bennée
d14a090e65
include/fpu/softfloat: implement float16_set_sign helper
Backports commit 78b5a3e653c90b56ba650f54c07fc18f7b7bd905 from qemu
2018-03-08 10:01:30 -05:00
Alex Bennée
380699fa35
include/fpu/softfloat: implement float16_chs helper
Backports commit 5f10aef521427b3909c24a0c7a82839b43f876e2 from qemu
2018-03-08 10:01:03 -05:00
Alex Bennée
facbc9ef66
include/fpu/softfloat: implement float16_abs helper
This will be required when expanding the MINMAX() macro for 16
bit/half-precision operations.

Backports commit 28136775cd99c628f7d7c642b04eb87f062efef8 from qemu
2018-03-08 10:00:30 -05:00
Alex Bennée
0eee5afd0e
target/*/cpu.h: remove softfloat.h
As cpu.h is another typically widely included file which doesn't need
full access to the softfloat API we can remove the includes from here
as well. Where they do need types it's typically for float_status and
the rounding modes so we move that to softfloat-types.h as well.

As a result of not having softfloat in every cpu.h call we now need to
add it to various helpers that do need the full softfloat.h
definitions.

Backports commit 24f91e81b65fcdd0552d1f0fcb0ea7cfe3829c19 from qemu
2018-03-08 09:58:47 -05:00
Alex Bennée
2a078de5e1
fpu/softfloat-types: new header to prevent excessive re-builds
The main culprit here is bswap.h which pulled in softfloat.h so it
could use the types in its CPU_Float* and ldfl/stfql functions. As
bswap.h is very widely included this added a compile dependency every
time we touch softfloat.h. Move the typedefs for each float type into
their own file so we don't re-build the world every time we tweak the
main softfloat.h header.

Backports commit cfd88fc6f2722def193f5ef271381d8f6e2a2526 from qemu
2018-03-08 09:52:15 -05:00
Alex Bennée
a34718da64
include/fpu/softfloat: remove USE_SOFTFLOAT_STRUCT_TYPES
It's not actively built and when enabled things fail to compile. I'm
not sure the type-checking is really helping here. Seeing as we "own"
our softfloat now lets remove the cruft.

Backports commit a9579fff616563ca34977af68c9646c8f7be1120 from qemu
2018-03-08 09:45:35 -05:00
Alex Bennée
8110bc8264
fpu/softfloat: implement float16_squash_input_denormal
This will be required when expanding the MINMAX() macro for 16
bit/half-precision operations.

Backports commit 210cbd4910ae9e41e0a1785b96890ea2c291b381 from qemu
2018-03-08 09:44:20 -05:00
Peter Maydell
19baeb5120
target/arm: Implement v8M MSPLIM and PSPLIM registers
The v8M architecture includes hardware support for enforcing
stack pointer limits. We don't implement this behaviour yet,
but provide the MSPLIM and PSPLIM stack pointer limit registers
as reads-as-written, so that when we do implement the checks
in future this won't break guest migration.

Backports commit 57bb31568114023f67680d6fe478ceb13c51aa7d from qemu
2018-03-08 09:42:04 -05:00
Peter Maydell
5812f7e3a3
target/arm: Implement writing to CONTROL_NS for v8M
In commit 50f11062d4c896 we added support for MSR/MRS access
to the NS banked special registers, but we forgot to implement
the support for writing to CONTROL_NS. Correct the omission.

Backports commit 6eb3a64e2a96f5ced1f7896042b01f002bf0a91f from qemu
2018-03-08 09:39:43 -05:00
Peter Maydell
09cfe29d5b
hw/intc/armv7m_nvic: Implement SCR
We were previously making the system control register (SCR)
just RAZ/WI. Although we don't implement the functionality
this register controls, we should at least provide the state,
including the banked state for v8M.

Backports register related changes in commit 24ac0fb129f9ce9dd96901b2377fc6271dc55b2b from qemu
2018-03-08 09:36:59 -05:00