* uc_reg_read & uc_reg_write now support ARM64 Neon registers
* Do not reuse uc_x86_xmm for uc_arm64_neon128. TODO: refactor both classes to use the same parent.
Providing a default level of parallelism is perfectly fine, but it
should also be possible to set higher or lower levels of parallelism
easily. This is particularly beneficial for people packaging the
software for Linux distributions.
Writing / reading to model specific registers should be as easy as
calling a function, it's a bit stupid to write shell code and run them
just to write/read to a MSR, and even worse, you need more than just a
shellcode to read...
So, add a special register ID called UC_X86_REG_MSR, which should be
passed to uc_reg_write()/uc_reg_read() as the register ID, and then a
data structure which is uc_x86_msr (12 bytes), as the value (always), where:
Byte Value Size
0 MSR ID 4
4 MSR val 8
* Remove glib from samples makefile
* changes to 16 bit segment registers needs to update segment base as well as segment selector
* change how x86 segment registers are set in 16-bit mode
* more appropriate solution to initial state of x86 segment registers in 16-bit mode
* remove commented lines
* Remove glib from samples makefile
* changes to 16 bit segment registers needs to update segment base as well as segment selector
* change how x86 segment registers are set in 16-bit mode
* unicorn: use waitable timer to implement usleep() on Windows
Signed-off-by: vardyh <vardyh.dev@gmail.com>
* atomic: implement barrier() for msvc
Signed-off-by: vardyh <vardyh.dev@gmail.com>
* Fix for MIPS issue.
* Sparc support added.
* M68K support added.
* Arm support ported.
* Fix issue with VS2015 shlobj.h file
* Arm issue fix.
* Finalise MSVC port.
* Changes to reduce size of libs
* Fix for MIPS issue.
* Sparc support added.
* M68K support added.
* Arm support ported.
* Fix issue with VS2015 shlobj.h file
* Arm issue fix.
* Finalise MSVC port.
