Alistair Francis 2ed6459e98 target/riscv: Add the mcountinhibit CSR ... 1.11 defines mcountinhibit, which has the same numeric CSR value as mucounteren from 1.09.1 but has different semantics. This patch enables the CSR for 1.11-based targets, which is trivial to implement because the counters in QEMU never tick (legal according to the spec). Backports commit 747a43e818dc36bd50ef98c2b11a7c31ceb810fa from qemu		2019-08-08 17:04:52 -04:00
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insn_trans	target/riscv: Add the privledge spec version 1.11.0	2019-08-08 17:03:33 -04:00
cpu_bits.h	target/riscv: Add the mcountinhibit CSR	2019-08-08 17:04:52 -04:00
cpu_helper.c	RISC-V: Fix a PMP check with the correct access size	2019-08-08 16:57:03 -04:00
cpu_user.h	Supply missing header guards	2019-06-12 10:59:10 -04:00
cpu-param.h	tcg: Split out target/arch/cpu-param.h	2019-06-10 19:35:46 -04:00
cpu.c	target/riscv: Restructure deprecatd CPUs	2019-08-08 17:01:22 -04:00
cpu.h	target/riscv: Add the privledge spec version 1.11.0	2019-08-08 17:03:33 -04:00
csr.c	target/riscv: Add the mcountinhibit CSR	2019-08-08 17:04:52 -04:00
fpu_helper.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
helper.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
insn16-32.decode	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-28 19:00:23 -04:00
insn16-64.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-28 19:20:36 -04:00
insn16.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-28 19:20:36 -04:00
insn32-64.decode	target/riscv: Convert RV64D insns to decodetree	2019-03-18 16:57:16 -04:00
insn32.decode	target/riscv: Name the argument sets for all of insn32 formats	2019-05-28 18:36:53 -04:00
instmap.h	Supply missing header guards	2019-06-12 10:59:10 -04:00
Makefile.objs	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-28 19:00:23 -04:00
op_helper.c	target/riscv: Use env_cpu, env_archcpu	2019-06-12 12:06:19 -04:00
pmp.c	RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off	2019-08-08 16:55:52 -04:00
pmp.h	RISC-V: Check for the effective memory privilege mode during PMP checks	2019-08-08 16:52:57 -04:00
translate.c	target/riscv: Split gen_arith_imm into functional and temp	2019-05-28 19:07:53 -04:00
unicorn.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
unicorn.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00