Commit Graph

7235 Commits

Author SHA1 Message Date
LIU Zhiwei
5ff1871e32 target/riscv: vector element index instruction
Backports 126bec3f6ff3379e1a49f4a7d36922bfd079a3cc
2021-03-07 12:29:13 -05:00
LIU Zhiwei
2f7cdaee7b target/riscv: vector iota instruction
Backports 78d90cfe859c8f5bd7baa0d41a4b5126e08eac24
2021-03-07 12:27:10 -05:00
LIU Zhiwei
ec24e09ce7 target/riscv: set-X-first mask bit
Backports 81fbf7daf2eccadd6480b90db95a2e8c410d4414
2021-03-07 12:25:09 -05:00
LIU Zhiwei
92d5ce9b66 target/riscv: vmfirst find-first-set mask bit
Backports 0db67e1c0c49011eb09c4f5b790eef15a2b4c351
2021-03-07 12:22:13 -05:00
LIU Zhiwei
782835889c target/riscv: vector mask population count vmpopc
Backports 2e88f551df8fe6af81c0f920b7341ae2c75d00f2
2021-03-07 12:20:01 -05:00
LIU Zhiwei
68765e92c0 target/riscv: vector mask-register logical instructions
c21f34aebfb15c112131e36f425986170a3fcae9
2021-03-07 12:16:44 -05:00
LIU Zhiwei
4cbb4ae73d target/riscv: vector widening floating-point reduction instructions
Backports 696b0c260a0312c865cd0e4a8f09d0b9f13b07c9
2021-03-07 12:12:49 -05:00
LIU Zhiwei
ebe125af76 target/riscv: vector single-width floating-point reduction instructions
Backports 523547f19e3914f11543e2da03907c724f15cd5e
2021-03-07 12:11:01 -05:00
LIU Zhiwei
798c1682f8 target/riscv: vector wideing integer reduction instructions
Backports bba718200b2d2aac6ab5031817f7125571c983a1
2021-03-07 12:09:15 -05:00
LIU Zhiwei
4b1e548fd0 target/riscv: vector single-width integer reduction instructions
Backports fe5c9ab1fc185e96bf7e034954127429ca74d386
2021-03-07 12:07:51 -05:00
LIU Zhiwei
e925927e23 target/riscv: narrowing floating-point/integer type-convert instructions
Backports 878d406ec28f945d262af4ffbea50b825d7a0825
2021-03-07 12:05:59 -05:00
LIU Zhiwei
0c80c49b1b target/riscv: widening floating-point/integer type-convert instructions
Backports 4514b7b12390525e59e335e7ca58fd44f6e69272
2021-03-07 12:02:56 -05:00
LIU Zhiwei
8b06759ba4 target/riscv: vector floating-point/integer type-convert instructions
Backports 921009732614fd620c75f05496597796719544cf
2021-03-07 12:00:36 -05:00
LIU Zhiwei
fabc8bab77 target/riscv: vector floating-point merge instructions
Backports 64ab5846974140118c64e4d94ff2696932a0a58b
2021-03-07 11:58:41 -05:00
LIU Zhiwei
f9c9716534 target/riscv: vector floating-point classify instructions
Backports 121ddbb36f17d24a7f39d6024d9b3145d154a98c
2021-03-07 11:55:45 -05:00
LIU Zhiwei
b859be12b9 target/riscv: vector floating-point compare instructions
Backports 2a68e9e568faddf4d689a37fa6895bcb8404a677
2021-03-07 11:47:51 -05:00
LIU Zhiwei
31978f270b target/riscv: vector floating-point sign-injection instructions
Backports 1d426b81f71eeeb1cbfec76c2f27ed0495719fb0
2021-03-07 11:43:47 -05:00
LIU Zhiwei
f7f0425a4d target/riscv: vector floating-point min/max instructions
Backports 230b53ddd706c8b18a6d9beed1a0153b276d7037
2021-03-07 11:42:05 -05:00
LIU Zhiwei
69c73cfc4e target/riscv: vector floating-point square-root instruction
Backports d9e4ce72a5a0f7c404156d40d3252d4d6a9d6a36
2021-03-07 11:40:04 -05:00
LIU Zhiwei
95a6d78121 target/riscv: vector widening floating-point fused multiply-add instructions
Backports 0dd509594fbd53fc9c3edc79bd7a575f079c3c87
2021-03-07 11:37:23 -05:00
LIU Zhiwei
42116609f0 target/riscv: vector single-width floating-point fused multiply-add instructions
Backports 4aa5a8fed4a21fe2e132a9a21b251aa95e19de80
2021-03-07 11:34:56 -05:00
LIU Zhiwei
14cbabde4f target/riscv: vector widening floating-point multiply
Backports f7c7b7cd293ca6f14f23cc2c14d6d23fc47a604d
2021-03-07 11:32:19 -05:00
LIU Zhiwei
5e4b142c31 target/riscv: vector single-width floating-point multiply/divide instructions
Backports 0e0057cbe2169195a08ae8247504e69f9b80542b
2021-03-07 11:30:14 -05:00
LIU Zhiwei
0de56731ae target/riscv: vector widening floating-point add/subtract instructions
eeffab2ec1b332a5eb2d2dcd2732cdb57179c6eb
2021-03-07 11:27:33 -05:00
LIU Zhiwei
06092b88b9 target/riscv: vector single-width floating-point add/subtract instructions
Backports ce2a0343f441f0ee949690eabae5ab600397e2eb
2021-03-05 09:50:56 -05:00
LIU Zhiwei
5fb589cdd7 target/riscv: vector narrowing fixed-point clip instructions
Backports 9ff3d28739b760970f5e542c74a033470dca3f9b
2021-03-05 09:34:11 -05:00
LIU Zhiwei
241deddb50 target/riscv: vector single-width scaling shift instructions
Backports 04a614062dd5fb43f00bd955f44f7a2c3def016d
2021-03-05 09:32:15 -05:00
LIU Zhiwei
e7582a5d74 target/riscv: vector widening saturating scaled multiply-add
Backports 0a1eaf0036442b2bfa69df7fad9a5f1d6a4984f2
2021-03-05 09:29:42 -05:00
LIU Zhiwei
e27aadfa4f target/riscv: vector single-width fractional multiply with rounding and saturation
Backports 9f0ff9e51480f8f1d2d7a62b11aa156fcdb4ef95
2021-03-05 09:26:56 -05:00
LIU Zhiwei
2343892c2e target/riscv: vector single-width averaging add and subtract
Backports b7aee4819206cbb7adfdb624d4f2fa9918c25d43
2021-03-05 09:25:09 -05:00
LIU Zhiwei
87db3eb130 target/riscv: vector single-width saturating add and subtract
Backports eb2650e35ec1ed60ff302ce3330bd6c770640833
2021-03-05 09:23:17 -05:00
LIU Zhiwei
025aa6fd39 target/riscv: vector integer merge and move instructions
Backports 	f020a7a14505d6996497693e63331ab609847d93
2021-03-05 09:20:34 -05:00
LIU Zhiwei
9d14cc8d35 target/riscv: vector widening integer multiply-add instructions
Backports 2b587b335050dbc0cb3823758341f145c0375312
2021-03-05 09:13:03 -05:00
LIU Zhiwei
58891e213d target/riscv: vector single-width integer multiply-add instructions
Backports 54df813a331d3badfb83604c36bef7cb1de4315a
2021-03-05 09:11:33 -05:00
LIU Zhiwei
436e092e36 target/riscv: vector widening integer multiply instructions
Backports 97b1cba39967251ab78b9d52fd9a4c62bb42d428
2021-03-05 09:09:08 -05:00
LIU Zhiwei
d144afdc45 target/riscv: vector integer divide instructions
Backports 85e6658cfe9d71cc207a710ffdf0e6546f8612aa
2021-03-05 09:05:00 -05:00
Lioncash
14d06ee38c sparc: Fix build 2021-03-05 08:54:43 -05:00
Lioncash
704353c758 mips: Fix build 2021-03-05 08:51:51 -05:00
Lioncash
dec4c70142 i386: Fix build 2021-03-05 08:35:14 -05:00
Lioncash
5436b713ce m68k: Fix build
A bunch of changes to the memory functions recently broke the build.
This fixes it.
2021-03-05 08:29:53 -05:00
Zheng Zhan Liang
dfd53d7573 tcg/i386: rdpmc: fix the the condtions
Backports c45b426acd1ad8e30fbe1b9af8c07b2889c28c6b
2021-03-04 18:50:48 -05:00
Chenyi Qiang
d7adcf1d7f target/i386: Add bus lock debug exception support
Bus lock debug exception is a feature that can notify the kernel by
generate an #DB trap after the instruction acquires a bus lock when
CPL>0. This allows the kernel to enforce user application throttling or
mitigations.

This feature is enumerated via CPUID.(EAX=7,ECX=0).ECX[bit 24].

Backports 06e878b413766778a53be3d25c0373a23679d039
2021-03-04 18:50:00 -05:00
Richard Henderson
d044062b26 target/arm: Enable MTE for user-only
Backports e32328645ed6fc4f20f0164dfc9ce1bf7e667cc4
2021-03-04 18:46:47 -05:00
Richard Henderson
c588c150e4 target/arm: Add allocation tag storage for user mode
Use the now-saved PAGE_ANON and PAGE_MTE bits,
and the per-page saved data.

Backports a11d3830d96ad8077440ce4e0aa60608f1f12dde
2021-03-04 18:46:13 -05:00
Richard Henderson
f03656b5c3 target/arm: Split out syndrome.h from internals.h
Move everything related to syndromes to a new file,
which can be shared with linux-user.

Backports 1fe27859427bd377a45708310947de54c687d9ff
2021-03-04 18:44:07 -05:00
Richard Henderson
84368d2d6d target/arm: Use the proper TBI settings for linux-user
We were fudging TBI1 enabled to speed up the generated code.
Now that we've improved the code generation, remove this.
Also, tidy the comment to reflect the current code.

The pauth test was testing a kernel address (-1) and making
incorrect assumptions about TBI1; stick to userland addresses.

Backports 16c849784873d10d0da257d698e391fddea1f0e4
2021-03-04 18:41:49 -05:00
Richard Henderson
de982a8346 target/arm: Improve gen_top_byte_ignore
Use simple arithmetic instead of a conditional
move when tbi0 != tbi1.

Backports 2169b5c6f7a791ef9c43c72412efaafae3245114
2021-03-04 18:39:43 -05:00
Peter Maydell
ab07f048d8 bswap.h: Remove unused float-access functions
The float-access functions stfl_*, stfq*, ldfl* and ldfq* are now
unused; remove them. (Accesses to float64 and float32 types can be
made with the ldl/stl/ldq/stq functions, as float64 and float32 are
guaranteed to be typedefs for normal integer types.)

Backports f930224fffead81e23e699517d1351e33890b6f7
2021-03-04 18:37:02 -05:00
Daniel Müller
642a683d7a target/arm: Correctly initialize MDCR_EL2.HPMN
When working with performance monitoring counters, we look at
MDCR_EL2.HPMN as part of the check whether a counter is enabled. This
check fails, because MDCR_EL2.HPMN is reset to 0, meaning that no
counters are "enabled" for < EL2.
That's in violation of the Arm specification, which states that

> On a Warm reset, this field [MDCR_EL2.HPMN] resets to the value in
> PMCR_EL0.N

That's also what a comment in the code acknowledges, but the necessary
adjustment seems to have been forgotten when support for more counters
was added.
This change fixes the issue by setting the reset value to PMCR.N, which
is four.

Backports d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621
2021-03-04 18:34:06 -05:00
Peter Maydell
2c926832bb accel/tcg: Add URL of clang bug to comment about our workaround
In cpu_exec() we have a longstanding workaround for compilers which
do not correctly implement the part of the sigsetjmp()/siglongjmp()
spec which requires that local variables which are not changed
between the setjmp and the longjmp retain their value.

I recently ran across the upstream clang bug report for this; add a
link to it to the comment describing the workaround, and generally
expand the comment, so that we have a reasonable chance in future of
understanding why it's there and determining when we can remove it,
assuming clang eventually fixes the bug.

Remove the /* buggy compiler */ comments on the #else and #endif:
they don't add anything to understanding and are somewhat misleading
since they're sandwiching the code path for *non*-buggy compilers.

Backports e6a41a045c298538d303cd8fe8d7ae29a0c066ad
2021-03-04 18:32:51 -05:00